IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

{"title":"A Novel Design Method for CML Frequency Divider Based on C/Id and G/Id and Application for Quadrature-Injection CML Frequency Dividers","authors":"Leilei Xiao;Yubing Li;Haifeng Chen;Yujia Chen;Zemeng Huang;Peng Ke;Xiuping Li","doi":"10.1109/TCSI.2024.3500017","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3500017","url":null,"abstract":"A novel design method for current-mode-logic (CML) frequency divider based on <inline-formula> <tex-math>${C/I} _{boldsymbol {d}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${G/I} _{boldsymbol {d}}$ </tex-math></inline-formula> is proposed. The design method proposes using <inline-formula> <tex-math>${C/I} _{boldsymbol {d}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${G/I} _{boldsymbol {d}}$ </tex-math></inline-formula> as independent design parameters, where C and G are the equivalent capacitance and conductance of coupling pair (C cell) and negative-<inline-formula> <tex-math>$boldsymbol {g}_{boldsymbol {m}}$ </tex-math></inline-formula> pair (N cell) in CML frequency dividers. Different from the traditional design method optimizing the maximum operating frequency (<inline-formula> <tex-math>$boldsymbol {f}_{textit {in,max} }$ </tex-math></inline-formula>) by adjusting the self-resonant frequency (<inline-formula> <tex-math>$boldsymbol {f}_{textit {SR} }$ </tex-math></inline-formula>), the proposed design method directly targets <inline-formula> <tex-math>$boldsymbol {f}_{textit {in,max} }$ </tex-math></inline-formula> and output amplitude (<inline-formula> <tex-math>$boldsymbol {V}_{textit {out} }$ </tex-math></inline-formula>) to obtain the <inline-formula> <tex-math>${C/I} _{boldsymbol {d}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${G/I} _{boldsymbol {d}}$ </tex-math></inline-formula> and solve the size and bias current of C and N cells, which realizes efficient design. Based on the proposed design method, several design examples are provided showing less than 3% error between the simulation results and design goals, and the proposed quadrature-injection CML (QI-CML) frequency divider is implemented and proven to have an improved sensitivity curve (SC). To validate the efficacy of our proposal, a frequency divider that can switch between differential-injection (DI) and QI is designed and fabricated in 110-nm CMOS process. For QI mode, the measured locking range (LR) is 141% (5-29 GHz) while consuming 5.47 mW. The achieved two figure of merits FOM<inline-formula> <tex-math>$_{textbf {Pdc}}$ </tex-math></inline-formula> and FOM<inline-formula> <tex-math>$_{textbf {A}}$ </tex-math></inline-formula> are 24.1 dB and 52.8 dB, respectively, which are superior to most published works.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1140-1151"},"PeriodicalIF":5.2,"publicationDate":"2024-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 3-D Multi-Precision Scalable Systolic FMA Architecture","authors":"Haotian Liu;Xicheng Lu;Xiaoyu Yu;Kai Li;Kaiyuan Yang;Haihang Xia;Sizhao Li;Tiantai Deng","doi":"10.1109/TCSI.2024.3497724","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3497724","url":null,"abstract":"Artificial Intelligence (AI) has almost become the default approach in a wide range of applications, such as computer vision, chatbots, and natural language processing. These AI-based applications require computing large-scale data with sufficient precision, typically in floating-point numbers, within a limited time window. A primary target for AI acceleration is matrix multiplication, mainly involving dot products through Multiply-Accumulate (MAC) operations. Current research employs the Fused Multiply-Add (FMA) operation, based on IEEE-754 Floating Point (FP) standard, to meet these requirements. However, current research focuses more on simplifying the internal digital circuits of the Processing Elements (PEs) performing FMA operations, rather than optimizing the FMA process specifically for MAC tasks. Current PE arrays often use a two-dimensional (2-D) systolic array design, without specific optimization for MAC operations, thus their parallelism is not fully utilized. Additionally, these designs lack reconfigurability and flexibility, leading to suboptimal performance on Field-Programmable Gate Arrays (FPGAs). Moreover, some designs adopt lower precision computing in AI inference for higher performance. However, some AI models still rely on high-precision computing to maintain the accuracy. Thus, multi-precision computing is commonly used in AI accelerators. To address these challenges, this paper proposes a novel Multi-Fused Multiply-Accumulate (MFMA) scheme and a corresponding three-dimensional (3-D) scalable systolic FP computing architecture. The MFMA scheme addresses the problem of the classical FMA scheme. It optimizes FMA for MAC operations with the Fused Multiply-Accumulate (FMAC) operation. Also, it combines multi-precision and mixed-precision FP computing methods for higher accuracy and lower overflow error. The proposed architecture integrates two 2-D systolic arrays into the PE for a 3-D systolic array, achieving higher parallelism and flexibility. The proposed scalable architecture can be customized to suit various FMAC operations. Compared with existing state-of-the-art FP architectures on FPGAs, our proposed architecture achieves 47%, 10%, and 159% energy efficiency improvements in FP32, FP16, and INT8 operations, respectively. Furthermore, our proposed architecture achieves energy efficiency improvements of 105%, 54%, and 262% under efficiency saturation conditions, outperforming the existing state-of-the-art design.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"265-276"},"PeriodicalIF":5.2,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"GSLP-CIM: A 28-nm Globally Systolic and Locally Parallel CNN/Transformer Accelerator With Scalable and Reconfigurable eDRAM Compute-in-Memory Macro for Flexible Dataflow","authors":"Yi Zhan;Wei-Han Yu;Ka-Fai Un;Rui P. Martins;Pui-In Mak","doi":"10.1109/TCSI.2024.3497187","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3497187","url":null,"abstract":"This article reports a globally systolic and locally parallel (GSLP) convolutional NN (CNN) and Transformer accelerator based on the scalable and reconfigurable (SR) embedded dynamic random-access memory (eDRAM) compute-in-memory (CIM) macro. It features: 1) a GSLP architecture employs systolic CIM macros with the reconfigurable inter-CIM network to support flexible dataflow, including weight stationary (WS), output stationary (OS), and Row stationary (RS); 2) an SR-CIM macro features reconfigurable weight/input/output memory ratio to maximize the related data reuse in different dataflow; 3) a high-density 3T eDRAM-CIM cell to further improve the density of the accelerator; 4) an area-efficient in-memory accumulator (IMA) to save the area and power overhead of the digital accumulation in each CIM macro. Prototyped in 28-nm CMOS process, the proposed GSLP-CIM accelerator exhibits a 4b peak throughput density of 0.16 TOPS/mm2 and a 4b peak compute energy efficiency of 3.55 TOPS/W. Specifically, evaluated with ResNet-50@ImageNet and ViT-B@ImageNet, this work reaches the system throughput of 24.5 and 5.66 inferences per second (IPS), the system throughput density of 19.3 IPS/mm2 and 4.46 IPS/mm2, the system compute energy efficiency of 423.9 inferences per watt (IPW) and 97.6 IPW, respectively.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1657-1667"},"PeriodicalIF":5.2,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient Single- and Dual-Band Rectifiers With Wide Range of Load Variations","authors":"Kai Biao Zhang;Bai Hua Zeng;Shao Yong Zheng;Ming Hua Xia","doi":"10.1109/TCSI.2024.3426081","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3426081","url":null,"abstract":"With the development of low-power devices, wireless power transfer and wireless energy harvesting techniques become increasingly important. As the critical component, the rectifier is required to maintain good performance under different scenarios. Most existing works focus on the improvement in bandwidth and input power range with a constant load value. However, the impedance of the driven devices cannot be predicted in practical applications, resulting in performance deterioration. Thus, an adaptive signal diversion approach is proposed to diver the injected signal to the parallel high and low load branches with distinct reactance compensation networks. This topology can be applied to both single- and dual-band rectifiers with simplicity and scalability in design. For validation, two rectifiers are designed, fabricated, and measured. The rectifier operating at 2.4 GHz achieves a load range of 0.16 k\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000 to 6 k\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000 (load variation ratio of 37.5). The dual-band rectifier working at 2.49 GHz and 5.14 GHz achieves load ranges from 0.21 to 5.4 k\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000 (load variation ratio of 25.7) and from 0.07 to 4.2 k\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000 (load variation ratio of 60), respectively. It can be found that the proposed rectifiers exhibit the largest load variation ratio with the minimum number of diodes and load compared with the state-of-the-art works.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"5873-5883"},"PeriodicalIF":5.2,"publicationDate":"2024-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142757860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Recoding Hybrid Stochastic Numbers for Preventing Bit Width Accumulation and Fault Tolerance","authors":"Yuhao Chen;Hongge Li;Yinjie Song;Xinyu Zhu","doi":"10.1109/TCSI.2024.3492054","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3492054","url":null,"abstract":"Stochastic computing is a promising technique for realizing high-performance computing owing to its extremely low hardware cost. However, the stochastic number (SN) has too many information redundancies, which leads to an exponential growth of latency. So, hybrid stochastic number (HSN) is proposed to solve the high-latency problem. Hybrid stochastic computing technology brings latency and efficiency advantages but faces the rigorous challenges of bit-width accumulation. In this study, a recoding method with high accuracy for HSN is proposed to reduce the bit width of HSN with only one clock delay. The hardware-resource savings in the polynomial circuit reach more than 80%. Then, the accuracy and fault tolerance of recoding are evaluated. The recoding method enables the pipeline structure in the pure HSN domain, preventing data conversion at the midpoint of the computation. Furthermore, based on the recoding method, a low-cost, bit-flip correction method for HSN is proposed, for realizing fault-tolerant data transmission and computation.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1243-1255"},"PeriodicalIF":5.2,"publicationDate":"2024-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 16–20 GHz Mixer First Receiver Architecture With Active Inductor-Based Low-Pass Elliptic Filter With High OOB-IIP3 in 180 nm CMOS","authors":"Gaurav Srivastava;Darshak Bhatt","doi":"10.1109/TCSI.2024.3488892","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3488892","url":null,"abstract":"This article introduces an innovative approach to realize a mixer-first receiver architecture, which comprises an N-path differential architecture realized through a passive-switching network, followed by a novel self-biased active inductor-based filter. This combination allows the circuit to achieve high pass-band to stop-band attenuation and the capability to adjust and achieve the desired bandwidth and occupy less area on-chip while maintaining a high selectivity level and rejecting unwanted signals. A noise-cancelling amplifier is placed between the N-path and active inductor-based low-pass elliptic filter to reduce the noise figure of the receiver. In addition to the filter, a novel self-biased baseband amplifier with a wide bandwidth is realized, followed by a buffer to derive a 50 ohms load. The LO signal generation for the proposed receiver is obtained by implementing a passive balun circuit that operates over a wideband followed by an on-chip polyphase filter and buffer. The proof of concept is validated by implementing a designed receiver with an N-path differential architecture followed by a novel active inductor-based low-pass third-order elliptic filter, which occupies less area and achieves high selectivity compared to a passive inductor based filter on 180-nm CMOS technology. The receiver operates within the frequency range of 16-20 GHz and achieves an instantaneous single sideband (SSB) bandwidth of 160 MHz. The proposed filter achieves a pass-band to stop-band attenuation of 47 dB with a Q of 140. Additionally, the receiver exhibits an in-band compression point at -5 dBm and in-band IIP3 of 4–6 dBm with out-of-band signal linearity greater than 10 dBm.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1152-1164"},"PeriodicalIF":5.2,"publicationDate":"2024-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Detection and Localization of Hardware-Assisted Intermittent Power Attacks in Mixed-Critical Systems","authors":"Sneha Agarwal;Keshav Goel;Mitali Sinha;Sidhartha Sankar Rout;Sujay Deb","doi":"10.1109/TCSI.2024.3493386","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3493386","url":null,"abstract":"Increasing complexity in power management (PMT) has led to a growing demand for third-party power managers (3PPMs) in Network-on-Chip based Mixed-Critical Systems (NoCMCS). However, a malicious 3PPM can exploit the interdependence of power amongst the router nodes to orchestrate well-structured, covert power attacks. Detection and localization of a malicious 3PPM is crucial to restore standard dynamic PMT and mitigating system performance degradation. We propose a novel, non-invasive, low-overhead, attack detection and localization framework for Hardware Trojan (HT)-assisted intermittent power attacks with random activation and deactivation phases in NoCMCS. In Phase-I, our framework makes use of pre-profiled thermal statistics of router nodes to detect any anomaly at runtime. In Phase-II, it leverages a self-aware methodology to locate the router nodes with malicious 3PPM. The proposed framework can detect multiple intermittent HTs in the network. Experimental evaluations on real-life benchmarks show that Phase-I of our framework is able to consolidate the search space of malicious nodes, reducing almost 90% of Phase-II’s computational workload. Phase-II localizes the malicious router nodes across various experimental scenarios with zero false positives. We also demonstrate the robustness of our framework for detecting and localizing malicious router nodes for different intermittent HTs with varying burst attacks over time.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"586-599"},"PeriodicalIF":5.2,"publicationDate":"2024-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143184448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Power Losses Optimization of MMCs Based on Quantum Genetic Algorithm for HVdc Transmission Application","authors":"Jifeng Zhao;Peidong Xu;Xinyue Wu;Jia Pei;Hong Fu;Yutan Li","doi":"10.1109/TCSI.2024.3486576","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3486576","url":null,"abstract":"Modular multilevel converters (MMCs) obtain widespread utilization in high-voltage direct current (HVdc) applications scenarios. The cost of power losses plays a significant part in MMC’s operating costs. Hence, this article proposes a quantum genetic algorithm-based power losses optimization control (QGA-PLOC). By comprehensively considering the power losses of the MMC, the quantum genetic algorithm determines the first-best value of the injected second circulating current magnitude and phase angle in the arm, as well as the optimal MMC power losses under given conditions. The quantum genetic algorithm incorporates the quantum state vector representation into genetic encoding and utilizes quantum logic gates for chromosome evolution, greatly improving the algorithm’s performance and significantly enhancing its computational efficiency and global optimization capability. Moreover, introducing the quantum genetic algorithm into the field of MMC power losses optimization offers a new path to address the acquisition of the optimal circulating current reference value in power loss optimization problems. MMC Simulation and experiment are also conducted, and the research results verify the effectiveness of the proposed QGA-PLOC for MMCs.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1902-1915"},"PeriodicalIF":5.2,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Efficient Asymmetric Outphasing Power Amplifier With Extended Back-Off Range for 5G Applications","authors":"Bai Hua Zeng;Wing Shing Chan;Shao Yong Zheng;Xin Yu Zhou;Shichang Chen","doi":"10.1109/TCSI.2024.3483933","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3483933","url":null,"abstract":"5G and future 6G wireless communication systems are pushing the practical limits on the modulation schemes that can be achieved in practice. These higher-level modulation schemes have further exacerbated the challenges in power amplifier (PA) design. One solution to linearly and efficiently amplify these modulation schemes that have high peak-to-average power ratios (PAPRs), is to use dual-input Outphasing PAs (OPAs). However, the output back-off (OBO) range of a conventional OPA is limited. To mitigate this issue, a new OPA based on an asymmetric architecture is proposed. This new asymmetric OPA is shown theoretically that the OBO range can be extended. To validate the proposal, an OPA is designed using two asymmetric sub-PAs and a modified Chireix combiner. The implemented OPA achieves drain efficiencies of 60.6% and 60% at saturation (44.1dBm) and at 8-dB OBO under CW excitation at 2.58 GHz, respectively. Measurement of the OPA using 20-MHz 5G NR signal with 8-dB PAPR yields an average drain efficiency of 58.3% with an adjacent channel power ratio (ACPR) below −45.1 dBc with digital pre-distortion (DPD).","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"143-154"},"PeriodicalIF":5.2,"publicationDate":"2024-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Analysis of a Coupled-Line-Based Load-Modulated Balanced Amplifier MMIC With Enhanced Bandwidth Performance","authors":"Jingyuan Zhang;Weichen Zhao;Baoguo Yang;Xu Yan;Yongxin Guo","doi":"10.1109/TCSI.2024.3489555","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3489555","url":null,"abstract":"This article presents the design theory and implementation of a fully integrated coupled-line-based load-modulated balanced amplifier (CLLMBA) monolithic microwave integrated circuit (MMIC). To facilitate the design, a novel design method is proposed for the CLLMBA to precisely control the load modulation and output power back-off (OBO) level by arranging the current ratio among the control amplifier (CA) and balanced amplifiers (BAs). Moreover, to further expand the working bandwidth, the coupled-line couplers are adopted in the CLLMBA. Subsequently, the physical dimensions and operating conditions of the three sub-amplifiers are selected accurately based on load modulation analysis at the fundamental frequency. It leads to properly modulated impedances and cancels the output matching networks for sub-amplifiers. Besides, meandering lange couplers are adopted by double metal layers and air-bridges for a compact layout. To validate the proposed techniques, a CLLMBA prototype is implemented and fabricated in a commercial 0.25-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m GaN HEMT process with the die size of \u0000<inline-formula> <tex-math>$3.1times 2.3$ </tex-math></inline-formula>\u0000 mm2. The measurement result exhibits a 38.1-39.3 dBm saturated output power with a 45.8%-57.6% saturated drain efficiency (DE), and a 31.7%-42.3% DE at 10-dB OBO from 4 to 6 GHz. Furthermore, under a 100 MHz orthogonal frequency division multiplexing (OFDM) signal with 8.5 dB peak-to-average power ratio (PAPR), the average DE is 32.8%-40.6% and the adjacent channel leakage ratio (ACLR) after digital predistortion is better than −47.5 dBc.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"111-124"},"PeriodicalIF":5.2,"publicationDate":"2024-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}