IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

{"title":"Prescribed Performance-Based Distributed Predefined Time Control for DC Microgrid Clusters","authors":"Mohamed Zaery;Syed Muhammad Amrr;Mohammad Ali;S. M. Suhail Hussain;Mohammad A. Abido","doi":"10.1109/TCSI.2025.3553702","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3553702","url":null,"abstract":"Interconnecting DC microgrids (MGs) into a cluster enhances renewable energy utilization and improves power supply reliability by enabling power flow between them. Effective management of DC MG clusters requires a control system designed for rapid response to fluctuating renewable source behavior and load demands. Traditional control methods lack the ability to pre-specify desired system performance, including convergence time and transient/steady-state behavior. Therefore, this work explores a prescribed performance function-based predefined time (PPF-PDT) control for optimizing the power dispatch of interconnected DC MGs according to the user-assigned preplanned desired performance. This scheme comprises secondary and tertiary control layers to handle the optimal operation for individual MGs and interconnected MGs, respectively, using a dual-layer sparse cyber network. In each MG, the secondary control matches the incremental costs of all distributed generation units while stabilizing the MG’s average voltage to the assigned voltage level within an adjustable predefined settling time independent of initial states. Adopting PPF significantly enhances transient and steady-state behavior, ensuring the tracking errors remain within desired performance limits. Additionally, distributed tertiary controllers across multiple MGs adjust their voltage references to optimize the exchanged power among them within a user-assigned tunable settling time. A thorough Lyapunov analysis verifies the stability of the proposed control algorithm within the predefined time and confines the tracking errors within acceptable bounds. Extensive simulation and experimental studies confirm the feasibility of the control strategy under various conditions.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 10","pages":"6262-6275"},"PeriodicalIF":5.2,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145210035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors","authors":"","doi":"10.1109/TCSI.2025.3550691","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3550691","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1975-1975"},"PeriodicalIF":5.2,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945524","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information","authors":"","doi":"10.1109/TCSI.2025.3550693","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3550693","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"C2-C2"},"PeriodicalIF":5.2,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945527","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Efficient and Reconfigurable Post-Quantum Crypto-Processor for SPHINCS+","authors":"Tianze Huang;Jiahao Lu;Dongsheng Liu;Zhixiang Luo;Chi Cheng;Aobo Li;Lei Chen;Shuo Yang;Jiaming Zhang;Xiang Li","doi":"10.1109/TCSI.2025.3544341","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3544341","url":null,"abstract":"SPHINCS+ is the sole hash-based digital signature scheme among the selected post-quantum cryptography (PQC) in 2022. This algorithm possesses the ability to resist attacks from both classical and quantum computers. Due to the extensive computations and different data widths for various parameters, its hardware implementation faces the weakness of long operation time, large area requirement, and low flexibility. This paper presents an efficient and reconfigurable SPHINCS+ processor. The proposed on-the-fly WOTS+ public key generation scheme with unified chain address generator accelerated the most time-consuming operations. This optimization achieves efficient resource utilization. A security switch mechanism resolves the bit misalignment among different data widths with resource reduction. Finally, we introduce a grouped subtree and segmented signature streaming scheme. They reduce the memory to 16k bytes. The processor consumes 29410 LUTs, 14090 FFs, 4 BRAMs on Artix-7 FPGA and achieves <inline-formula> <tex-math>$1.04times/2.41times $ </tex-math></inline-formula> ATPs (area-time-product) optimizations in Sign/Verify with the advantage of supporting all security levels of SPHINCS+.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2252-2262"},"PeriodicalIF":5.2,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation","authors":"Meng Guo;Qi Wu;Chuanning Wang;Yangcan Zhou;Shaowei Wang;Chuan Zhang;Zhongfeng Wang;Jun Lin","doi":"10.1109/TCSI.2025.3547319","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3547319","url":null,"abstract":"Channel estimation (CE) is a critical component in the massive multi-input multi-output (MIMO) communication systems. Compared with conventional CE algorithms, deep learning (DL)-based approach becomes a promising alternative, due to its capability of offering enhanced performance and robustness across diverse scenarios. However, efficient DL-based CE algorithms have two key properties that make them challenging for implementation in existing architectures at the edge side: the diversity of deep neural networks (DNNs) and CE strategies, and the involvements of multiple computation-intensive tasks that compass conventional signal processing, artificial intelligence (AI) inference, and online learning. To address these challenges, a domain-specific processor based on an extended RISC-V instruction set architecture (ISA) is proposed to perform these DL-based CE algorithms. First, a dedicated RISC-V ISA extension is developed to support all essential operations required by a DL-based CE algorithm, such as matrix inversion, in a flexible manner. Building on the customized ISA extension, a highly adaptable and scalable RISC-V processor is developed, featuring scalar and vector posit arithmetic units to alleviate high computational and memory demands of DNNs during both inference and training phase. Additionally, a coarse-grained matrix accelerator is integrated to expedite various matrix operations ensuring high throughput. In this way, both high flexibility and computational efficiency are achieved. Finally, our processor is implemented on a TSMC 28-nm technology. Implementation results show that the processor achieves a speedup of <inline-formula> <tex-math>$5.16sim 6.80times $ </tex-math></inline-formula> for all matrix operations compared with the state-of-the-art work. Moreover, the proposed processor provides an area efficiency improvement of <inline-formula> <tex-math>$1.61times $ </tex-math></inline-formula> and an energy efficiency enhancement of <inline-formula> <tex-math>$6.6sim 15.4times $ </tex-math></inline-formula> compared to the open-source vector processor Ara. Notably, this work is the first RISC-V domain-specific processor tailored for diverse DL-based CE algorithms.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2380-2393"},"PeriodicalIF":5.2,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A VM-Terminated PAM-3 Transmitter Using Floating Middle Level With Enhanced Signal Integrity and Energy Efficiency for Low-Power Memory Interfaces","authors":"Chanheum Han;Ki-Soo Lee;Jun-Cheol Lee;Joo-Hyung Chae","doi":"10.1109/TCSI.2025.3552405","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3552405","url":null,"abstract":"This paper introduces a three-level pulse amplitude modulation single-ended transmitter using V_M (half of <inline-formula> <tex-math>$text{V}_{mathrm {DDQ}}$ </tex-math></inline-formula>) termination, designed for next-generation low-power memory interfaces. The proposed signaling strategy, based on the V_M termination, improves signal integrity by reducing signaling current by 41.05% while maintaining the same voltage swing compared to existing V_SS-terminated structures for low-power memory interfaces. This reduction in signaling current effectively decreases simultaneous switching output noise. Additionally, this approach alleviates the voltage headroom limitation and enables pre-emphasis adoption, resulting in a larger voltage swing and reduced power consumption compared to de-emphasis. The voltage difference between the drain and source of each pull-up and pull-down driver is balanced, achieving a good ratio of level mismatch (RLM). Moreover, the three-step ZQ calibration and transmission gate-based receiver-side V_M termination help achieve accurate on-resistance and improve output linearity, reducing signal reflection. The prototype chip, fabricated using a 65-nm CMOS process, has an area of 0.0184 mm². It achieves a data rate of 22.5 Gb/s with an energy efficiency of 0.86 pJ/bit and a measured RLM of 99.2%.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2653-2663"},"PeriodicalIF":5.2,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Inductor-First Tri-Path Hybrid Buck Converter With Reduced Inductor Current Suitable for USB Power Delivery Adapter","authors":"Zhitong Chen;Yufei Sun;Xiaoya Fan;Yanzhao Ma","doi":"10.1109/TCSI.2025.3551087","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3551087","url":null,"abstract":"This paper presents an inductor-first tri-path (IFTP) buck converter suitable for USB power delivery adapter to charge 1-2 cell battery. The proposed topology adopts the inductor-first strategy and the tri-path strategy of one inductor path and two capacitor paths to extend the output voltage conversion range, realize the continuous input current, eliminate the input EMI noise, and reduce the inductor current. In addition, a phase-interleaved symmetric inductor-first tri-path (PIS-IFTP) buck converter is proposed to alleviate the inrush current in the flying capacitor under extreme duty cycle of IFTP converter, while further reducing inductor current ripple. Two experimental prototypes for 9 V input to 3-8.4 V ouput have been developed, demonstrating excellent ability of IFTP and PIS-IFTP topologies to reduce inductor current and achieve continuous input current over the whole duty cycle and load range. The experimental results validate that the prototypes provide a wide voltage conversion range of 1/3-1 and a maximum output current of 1.8 A. The peak efficiency of IFTP is 93% at <inline-formula> <tex-math>$V_{OUT} ,, =6.6$ </tex-math></inline-formula> V, while the peak efficiency of PIS-IFTP is 94.5% at <inline-formula> <tex-math>$V_{OUT} ,, =3.3$ </tex-math></inline-formula> V.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 10","pages":"6251-6261"},"PeriodicalIF":5.2,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145210138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mixed-Signal Silicon Photomultiplier With Reconfigurable Pulse Shaper for Background Light Rejection","authors":"Arianna Morciano;Massimo Gandola;Matteo Perenzoni;Leonardo Gasparini;Antonio Vincenzo Radogna;Stefano D'Amico","doi":"10.1109/TCSI.2025.3549682","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3549682","url":null,"abstract":"This paper presents a mixed-signal Silicon Photomultiplier with integrated front-end, including a reconfigurable Pulse Shaper. Each Silicon Photon Avalanche Diode of the msSiPM converts a photon into a programmable current pulse. Then, all analog current signals are collected by a transimpedance amplifier which provides an output voltage proportional to the number of triggered SPADs. By properly tuning the shape of the current pulses, the proposed msSiPM rejects the background light and optimizes the Signal-to-Noise Ratio. As the architecture is mostly digital, msSiPM consumes a low static power consumption, equal to 428 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>W. The receiver is composed by a <inline-formula> <tex-math>$20 ,, times 20$ </tex-math></inline-formula>-pixel array, and it is fabricated in a 0.11 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS technology reaching a pixel fill factor equal to 32.8%. Measurements have been carried out under different background photon fluxes, one stronger and one weaker, corresponding to 4.15 and 2.15 GPhotons/s at the SiPM, demonstrating strong background rejection in both conditions. In addition, a SNR maximization has been verified. Analytical models for SNR and Signal-to-Background Ratio have been presented, showing a good matching with experimental results.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 7","pages":"3126-3137"},"PeriodicalIF":5.2,"publicationDate":"2025-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient Design and Implementation of Scale-Free CORDIC With Mutually Exclusive Micro-Rotations","authors":"Pramod Kumar Meher;Supriya Aggarwal","doi":"10.1109/TCSI.2025.3549974","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3549974","url":null,"abstract":"In this paper, a new approach to the design of a micro-rotation set for scale-free CORDIC is proposed. The sine and cosine functions of all the micro-rotation angles are realized by a simple shift or a shift-add operations which significantly reduces the hardware complexity. Besides, the micro-rotation set (except the first one) is designed to form mutually exclusive pairs. As a result of mutually exclusive micro-rotations, it is possible to reduce the required number of iterations to almost half for a given precision. Apart from that, the latency, as well as, the hardware complexity are also significantly reduced. A 9-bit fractional accuracy is obtained with just 5 iterations as against 13 iterations required by the conventional CORDIC. Suitable threshold angles are proposed to decide, using low-complexity comparators, whether a micro-rotation should be executed in a given iteration or can be skipped. The proposed circuits to determine the rotation conditions for different iterations involve either 2-bit or 3-bit comparators. The CORDIC circuit based on the proposed set of micro-rotations is shown to converge for any given angle of rotation. Furthermore, the proposed design involves significantly less logic, computation time, and latency than the best of the scale-free CORDIC circuits. When implemented on Xilinx FPGA (Field Programmable Gate Arrays), it requires 20% less area, offers higher operating frequency, and saves close to 19% power and 20% energy per computation over the latter.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2243-2251"},"PeriodicalIF":5.2,"publicationDate":"2025-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Neural-Network-Assisted Chaos-NOMA Scheme","authors":"Gabriel Carlini;Carlos E. C. Souza;Daniel P. B. Chaves;Cecilio Pimentel","doi":"10.1109/TCSI.2025.3549933","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3549933","url":null,"abstract":"We propose a non-orthogonal multiple access (NOMA) scheme based on three-dimensional chaotic attractors, which we denote chaos-NOMA. In this system, the chaotic signals transmitted by each user are generated from the state variables of the attractor. We employ a principal component analysis algorithm for dimensionality reduction and obtain an orthonormal basis and a signal constellation for the chaotic signals. The dynamical properties of these signals result in the transmission of time-varying waveforms, modeled as an intrinsic noise. Depending on factors such as the number of users and the power difference of the transmitted signals, this intrinsic noise can lead to a performance curve exhibiting an error floor. We propose a neural network architecture coupled to the demodulator to mitigate the impact of the intrinsic noise.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 7","pages":"3464-3473"},"PeriodicalIF":5.2,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144550358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}