IEEE Transactions on Circuits and Systems I: Regular Papers最新文献_第8页

Modular Expansion Method for Wireless Power Transfer Systems With Arbitrary Topologies 具有任意拓扑结构的无线电力传输系统的模块化扩展方法

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-27 DOI: 10.1109/TCSI.2024.3438563

Chao Cui;Chunbo Zhu;Xin Gao;Shumei Cui;Qianfan Zhang;C. C. Chan

{"title":"Modular Expansion Method for Wireless Power Transfer Systems With Arbitrary Topologies","authors":"Chao Cui;Chunbo Zhu;Xin Gao;Shumei Cui;Qianfan Zhang;C. C. Chan","doi":"10.1109/TCSI.2024.3438563","DOIUrl":"10.1109/TCSI.2024.3438563","url":null,"abstract":"Modular parallel inverter technology can enhance the power level and redundancy of wireless power transfer (WPT) systems, contributing to standardized production. It serves as an effective method for realizing high-power systems. However, inappropriate selection of compensation components can negatively affect the system’s efficiency, power factor, and the flexibility of modularization. This paper analyzes two key properties of modular-parallel-inverter WPT (MPI-WPT) systems: module number flexibility and modular deviation suppression. Firstly, to assess the modular deviation suppression of the system, its definition and calculation method are provided. Secondly, the expansion condition to achieve modular flexibility is examined, highlighting that the modular system needs to be a fully resonant system. Subsequently, an expansion design methodology from a single WPT system to an MPI-WPT system is proposed, ensuring the preservation of the original properties of the system during its extension. Finally, the parallel characteristics of MPI-WPT systems were experimentally verified.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4824-4836"},"PeriodicalIF":5.2,"publicationDate":"2024-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Efficient FPGA-Based Dilated and Transposed Convolutional Neural Network Accelerator 基于 FPGA 的高效稀释和变换卷积神经网络加速器

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-27 DOI: 10.1109/TCSI.2024.3428636

Tsung-Hsi Wu;Chang Shu;Tsung-Te Liu

{"title":"An Efficient FPGA-Based Dilated and Transposed Convolutional Neural Network Accelerator","authors":"Tsung-Hsi Wu;Chang Shu;Tsung-Te Liu","doi":"10.1109/TCSI.2024.3428636","DOIUrl":"10.1109/TCSI.2024.3428636","url":null,"abstract":"This work presents a Field Programmable Gate Array (FPGA)-based deep neural network (DNN) accelerator that can maintain consistently high efficiency when executing various neural network architectures, including convolutional neural network (CNN), transposed and dilated convolution (TD-convolution) operations for modern computer vision (CV) tasks. To deal with the utilization degradation issue with a large processing unit (PE) array, a 3-D mapping strategy that adaptively tailors different layer configurations is proposed to optimize the parallelism dimensions of the PE, which significantly increases the hardware utilization to enhance the accelerator efficiency. Moreover, to minimize the implementation and performance overhead resulting from the TD-convolution operations, a unified processing flow is proposed to realize an integrated operation of traditional and TD-convolution. This allows the accelerator to bypass redundant zero operations, further boosting overall efficiency. The 4096-PE accelerator implementation on Intel Stratix 10 FPGA achieves a throughput performance of 2.597–2.870 TOPS with an efficiency of 0.63-0.70 GOPS/DSP across various DNN networks. This represents \u0000<inline-formula> <tex-math>$1.72times $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$1.73times $ </tex-math></inline-formula>\u0000 improvement in throughput and efficiency, respectively, compared to the state-of-the-art designs.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"5178-5186"},"PeriodicalIF":5.2,"publicationDate":"2024-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis and Design of a 21.2-to-25.5-GHz Triple-Coil Transformer-Coupled QVCO 21.2 至 25.5 千兆赫三线圈变压器耦合 QVCO 的分析与设计

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-22 DOI: 10.1109/TCSI.2024.3445179

Ya Zhao;Chao Fan;Jun Yin;Pui-In Mak;Li Geng

{"title":"Analysis and Design of a 21.2-to-25.5-GHz Triple-Coil Transformer-Coupled QVCO","authors":"Ya Zhao;Chao Fan;Jun Yin;Pui-In Mak;Li Geng","doi":"10.1109/TCSI.2024.3445179","DOIUrl":"10.1109/TCSI.2024.3445179","url":null,"abstract":"This paper reports a triple-coil transformer-coupled quadrature voltage-controlled oscillator (TC-QVCO), which inherently provides the quadrature signal without using the noisy active-coupling transistors. The determinate correlation of tank voltages is verified by utilizing the initial state to facilitate the oscillation state analysis. Thus, the TC-QVCO would operate without the oscillation mode ambiguity. Additionally, thanks to the triple-coil transformer coupling, a large source coil \u0000<inline-formula> <tex-math>$L_{S}$ </tex-math></inline-formula>\u0000 aids in achieving in-phase coupling for phase noise (PN) improvement, and the intensified coupling factor \u0000<inline-formula> <tex-math>$k_{gd}$ </tex-math></inline-formula>\u0000 benefits reducing the PN and the quadrature phase error simultaneously. Therefore, our TC-QVCO would alleviate the tradeoff between PN and quadrature phase accuracy via using a large \u0000<inline-formula> <tex-math>$L_{S}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$k_{gd}$ </tex-math></inline-formula>\u0000. The proposed QVCO prototyped in 65-nm CMOS exhibits a superior FoM\u0000<inline-formula> <tex-math>$_{text {@10MHz}}$ </tex-math></inline-formula>\u0000 (180.1 to 182.2 dBc/Hz) over a 18.2% frequency tuning range (21.2 to 25.5 GHz), and the estimated quadrature phase error <0.8°.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4538-4549"},"PeriodicalIF":5.2,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 0.5-V 0.02% THD Bulk-Driven OTA for Continuous-Time Applications in 180 nm CMOS 用于 180 nm CMOS 连续时间应用的 0.5 V 0.02% THD 块状驱动 OTA

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-22 DOI: 10.1109/TCSI.2024.3443452

Yangxin Xiang;Huajun Yao;Minghao Jiang;Junkun Chen;Yongzhen Chen;Jiangfeng Wu

{"title":"A 0.5-V 0.02% THD Bulk-Driven OTA for Continuous-Time Applications in 180 nm CMOS","authors":"Yangxin Xiang;Huajun Yao;Minghao Jiang;Junkun Chen;Yongzhen Chen;Jiangfeng Wu","doi":"10.1109/TCSI.2024.3443452","DOIUrl":"10.1109/TCSI.2024.3443452","url":null,"abstract":"This paper introduces a 0.5-V, two-stage, pseudo-differential bulk-driven operational transconductance amplifier with high gain and linearity for low-power continuous-time applications. The input stage’s common-mode feedback utilizes a linear resistor detector with a conductance reduction cross-coupled pair to mitigate the loading effect of the common-mode detector resistor at ultra-low power operations. Temperature dependence of the conductance reduction circuit is compensated. The impact of the conductance reduction circuit on linearity performance is explored. The output stage employs a class-AB topology and utilizes a phase lead compensator to stabilize the OTA. Implemented in 180 nm CMOS technology, this OTA achieves a DC gain and slew rate of 68 dB and 26.1 V/\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 s, respectively, under a capacitive load of 10 pF. The total power consumption is \u0000<inline-formula> <tex-math>$34.2~mu $ </tex-math></inline-formula>\u0000 W. With unit gain feedback configuration, the measured total harmonic distortion is only 0.02% at an output amplitude of 500 mVpp. Test results validate the proposed circuit, positioning it competitively compared to state-of-the-art designs.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4420-4433"},"PeriodicalIF":5.2,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook 使用 16 点编码本实现上行链路 MIMO-SCMA 检测的组近似期望传播算法

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-20 DOI: 10.1109/TCSI.2024.3439616

Mei-Hsuan Chang;Pei-Yun Tsai

{"title":"Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook","authors":"Mei-Hsuan Chang;Pei-Yun Tsai","doi":"10.1109/TCSI.2024.3439616","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3439616","url":null,"abstract":"The complexity of conventional massage propagation algorithm (MPA) for detection of sparse code multiple access (SCMA) grows exponentially as the size of the codebook increases, posing a challenge for hardware implementation of large-size codebooks. Expectation propagation algorithm (EPA) has shown its superiority owing to its linear complexity with respect to the codebook size. In this paper, we propose log-domain group-approximate EPA (GA-EPA) for further complexity reduction. The mother constellation points are partitioned into several groups, which can simplify the calculation of posterior probability. Compared to conventional EPA, log-domain GA-EPA can reduce approximately 76.4% of multiplications and 53.8% of divisions for MIMO-SCMA signal detection. A GA-EPA detector is then designed in 40nm CMOS technology, we use customized floating-point to shorten word-lengths and to exploit the property of exponential function for accomplishing 17% total area reduction and more than 99% table reduction. From the synthesis results, our design for MIMO-SCMA detection with 16-point codebook from 4 receiving antennas can achieve a throughput of 364Mbps at an operating frequency of 167MHz. Compared to the prior MPA-related implementations, our work outperforms in normalized hardware efficiency and demonstrates a promising solution for large codebook cardinality.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4753-4766"},"PeriodicalIF":5.2,"publicationDate":"2024-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142368459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hardware-Efficient SoftMax Architecture With Bit-Wise Exponentiation and Reciprocal Calculation 采用比特-明智幂级数和倒数计算的硬件高效 SoftMax 架构

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-20 DOI: 10.1109/TCSI.2024.3443270

Jeongmin Kim;Sungho Kim;Kangjoon Choi;In-Cheol Park

{"title":"Hardware-Efficient SoftMax Architecture With Bit-Wise Exponentiation and Reciprocal Calculation","authors":"Jeongmin Kim;Sungho Kim;Kangjoon Choi;In-Cheol Park","doi":"10.1109/TCSI.2024.3443270","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3443270","url":null,"abstract":"The SoftMax function is one of the activation functions used in deep neural networks (DNN) to normalize input values to the range of (0,1). With the advent of DNN models including the Transformer, operations utilizing SoftMax have gained significant attention, and the efficient hardware implementation of such operations has become a prominent issue in hardware realization. Implementing SoftMax often involves exponential and division operations, which can be a significant bottleneck in terms of hardware cost and performance. Various efforts have been made to address this challenge, and this paper introduces a novel approach to efficiently implement SoftMax. In most previous works, the maximum input value is subtracted from all the input values to ensure numerical stability. In the proposed approach, the maximum value is replaced with a different value to reduce the hardware complexity with ensuring numerical stability. Additionally, in exponential operations, simple Look-Up Tables (LUTs) with only one entry each are used for bit-wise calculations, and the reciprocal of the total exponential sum is computed to replace division with multiplication. Applying the proposed methods reduces the computational complexity significantly compared to the previous log-sum-exp approach. As a result, the proposed 8-bit SoftMax accelerator achieves a high operating frequency of 3.12GHz and a high throughput of 25G inputs/s. It also improves area efficiency and power consumption by at least 2 times. From an accuracy perspective, furthermore, it is associated with similar or even better accuracy compared to previous works.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4574-4585"},"PeriodicalIF":5.2,"publicationDate":"2024-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142377007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Generalized Switched-Capacitor-Based Hybrid Multilevel Inverter With Reduced Components Count and Inrush Current 基于通用开关电容器的混合多电平逆变器可减少元件数量和浪涌电流

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-20 DOI: 10.1109/TCSI.2024.3443188

Niraj Kishore;Kapil Shukla;Nitin Gupta

{"title":"Generalized Switched-Capacitor-Based Hybrid Multilevel Inverter With Reduced Components Count and Inrush Current","authors":"Niraj Kishore;Kapil Shukla;Nitin Gupta","doi":"10.1109/TCSI.2024.3443188","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3443188","url":null,"abstract":"This article presents a novel topology for a three-phase switched-capacitor (SC) based hybrid multilevel inverter (HMLI) with boosted output voltage. The proposed topology employs generalised structure of SC-based inverters (SCBIs) to improve the output voltage levels utilising SC cells. The proposed structure additionally features self-charging and voltage-balancing capabilities of the SCs, without the need of auxiliary circuit/sensor. A modified PWM (MPWM) technique is utilized to modulate the system. The MPWM results in improved output voltage profile and reduction in voltage ripple across the SCs. The proposed structure is quantitatively compared with the state-of-the-art topologies to demonstrate its advantages in the terms of reduced components count, low maximum blocking voltage (MBV), low total standing voltage (TSV), lessened total harmonic distortion (THD), lowered cost function (CF) per level, and boosted output voltage. The performance of the proposed topology is verified in MATLAB/Simulink environment and a laboratory prototype is developed to confirm the feasibility to operate at steady-state and dynamic conditions.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4887-4896"},"PeriodicalIF":5.2,"publicationDate":"2024-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142368391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus 基于 E-Tree 的超大规模 SRAM 设计与优化，重点关注互连问题

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-19 DOI: 10.1109/TCSI.2024.3438164

Zhenlin Pei;Hsiao-Hsuan Liu;Mahta Mayahinia;Mehdi B. Tahoori;Francky Catthoor;Zsolt Tőkei;Dawit Burusie Abdi;James Myers;Chenyun Pan

{"title":"Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus","authors":"Zhenlin Pei;Hsiao-Hsuan Liu;Mahta Mayahinia;Mehdi B. Tahoori;Francky Catthoor;Zsolt Tőkei;Dawit Burusie Abdi;James Myers;Chenyun Pan","doi":"10.1109/TCSI.2024.3438164","DOIUrl":"10.1109/TCSI.2024.3438164","url":null,"abstract":"SRAM performance is highly dominated by interconnects as technology scales down because of the significant parasitic resistance and capacitance in the interconnect. This paper introduces a framework for the co-design of technology, interconnect, and cache memory with tag array overhead, to optimize the performance of cache memory using a variety of emerging interconnect technologies. In addition, we introduce an innovative E-Tree interconnect aimed at further decreasing the average interconnect length with the consideration of realistic workloads and benchmark against its traditional H-Tree counterparts in terms of various performance metrics, such as energy-delay-area product (EDAP) or energy-delay product (EDP) in the SRAM cache memory system. A comprehensive investigation of design space is conducted, employing realistic, deeply scaled subarray designs across a range of cutting-edge technology nodes. Furthermore, the case study examines various cache memory system design parameters to assess the true potential of emerging interconnect technologies in achieving optimal performance at the cache memory system.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4597-4610"},"PeriodicalIF":5.2,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Balanced CMOS Compatible Ternary Memristor-NMOS Logic Family and Its Application 平衡 CMOS 兼容型三元 Memristor-NMOS 逻辑系列及其应用

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-19 DOI: 10.1109/TCSI.2024.3441852

Xiaoyuan Wang;Xinhui Chen;Jiawei Zhou;Gang Liu;Sung-Mo Kang;Sanjoy Kumar Nandi;Robert G. Elliman;Herbert Ho-Ching Iu

{"title":"A Balanced CMOS Compatible Ternary Memristor-NMOS Logic Family and Its Application","authors":"Xiaoyuan Wang;Xinhui Chen;Jiawei Zhou;Gang Liu;Sung-Mo Kang;Sanjoy Kumar Nandi;Robert G. Elliman;Herbert Ho-Ching Iu","doi":"10.1109/TCSI.2024.3441852","DOIUrl":"10.1109/TCSI.2024.3441852","url":null,"abstract":"Balanced ternary digital logic circuits based on memristors and MOSFET devices are introduced. First, balanced ternary minimum gate TMIN, maximum gate TMAX and ternary inverters are designed and verified by simulation. Next, logic circuits such as ternary encoders, decoders and multiplexers are designed using these three basic gates. For further validation, a ternary 3–1 encoder was hardware-implemented successfully using in-house fabricated memristors and MOS transistors. Two different design approaches, namely the decoder-based method and the multiplexer-based method are introduced and applied to realize combinational logic circuits such as balanced ternary half-adder, multiplier, and numerical comparator. We simulate the circuits using 50nm CMOS technology parameters and BSIM models and present comparisons and analyses of the two design methods in view of the power consumption and component device counts, which can guide subsequent research and development of integrated multi-valued logic circuits. The decoder-based method has advantages both in terms of component numbers and power consumption, but the multiplexer-based method has the advantages of being based on a simple operating principle and ease of implementation.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4560-4573"},"PeriodicalIF":5.2,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Online Monitoring Method for Capacitor Condition of Cascaded H-Bridge STATCOM Based on Sensorless Capacitor Voltage Detection 基于无传感器电容器电压检测的级联 H 桥 STATCOM 电容器状态在线监测方法

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-19 DOI: 10.1109/TCSI.2024.3407125

Jikai Chen;Xinhai Chang;Chuang Liu;Haoru Li

{"title":"An Online Monitoring Method for Capacitor Condition of Cascaded H-Bridge STATCOM Based on Sensorless Capacitor Voltage Detection","authors":"Jikai Chen;Xinhai Chang;Chuang Liu;Haoru Li","doi":"10.1109/TCSI.2024.3407125","DOIUrl":"10.1109/TCSI.2024.3407125","url":null,"abstract":"In order to achieve the stable dc voltage support during the process of reactive power compensation, the cells within the chain of CHB STATCOM are equipped with high-capacity capacitors (along with dc voltage detection devices). However, over time, these capacitors exhibit varying degrees of aging, leading to discrepancies in capacitance reduction or variations in the equivalent series resistance (ESR) values, which not only complicates the task of balancing the capacitor voltages across the chain’s cells, but also increases the risk of device overvoltage. To address the problem, an online monitoring method for capacitor conditions based on sensorless capacitor voltage detection is proposed. Initially, the mapping relationship between the capacitance and its corresponding voltages is established on basis of the cell’s switching state and the principle of energy conservation. Subsequently, the capacitance estimation algorithm is constructed based on the data from sensorless capacitor voltage detection. In addition, the factors contributing to capacitance estimation errors are analyzed, and potential solutions are offered. This method facilitates the detection of each cell’s dc voltage and capacitance variations, while eliminating additional costs related to dc sensors and its associated communication devices. Ultimately, the effectiveness of the proposed online monitoring method is verified by MatLab/Simulink simulation and the StarSim experimental platform.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"5628-5635"},"PeriodicalIF":5.2,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0