IEEE Transactions on Circuits and Systems I: Regular Papers最新文献_第8页

Memristor-Emulator-Based Crossbar Array for Object Detection and Recognition 基于忆阻器仿真器的交叉棒阵列目标检测与识别

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-03 DOI: 10.1109/TCSI.2025.3553058

Jagveer Singh Verma;Prashant Kumar;Basit Shafat Makhdoomi;Rajeev Kumar Ranjan;Sung-Mo Kang

{"title":"Memristor-Emulator-Based Crossbar Array for Object Detection and Recognition","authors":"Jagveer Singh Verma;Prashant Kumar;Basit Shafat Makhdoomi;Rajeev Kumar Ranjan;Sung-Mo Kang","doi":"10.1109/TCSI.2025.3553058","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3553058","url":null,"abstract":"Object detection and recognition are crucial for autonomous vehicles, surveillance systems, and human-computer interaction. We present a new fully complementary metal-oxide semiconductor (CMOS) circuit-based system for object detection and recognition using a Spiking Neural Network (SNN). Our holistic CMOS circuit integrates neuromorphic elements, including a leaky integrate-and-fire (LIF) neuron model, spike time-dependent plasticity (STDP) memristor synapse, and basic analog and digital building blocks. The learning mechanism is manifested by a completely different approach based on an array of XOR gates to recognize six different objects with <inline-formula> <tex-math>$256 times 6$ </tex-math></inline-formula> size crossbar arrays. This is the first-ever recognition mechanism of its kind. We also perform handwritten digit recognition using a <inline-formula> <tex-math>$64 times 4$ </tex-math></inline-formula> size array using grayscale conversion. The proposed system’s robustness is validated through process corner simulations, noise analysis, and temperature analysis. We also show the accuracy of our design for the digit recognition task using a confusion matrix plot, and the accuracy turns out to be 82.5 %. Our pioneering approach using a CMOS memristor-emulator STDP crosspoint array-based architecture achieves minimal energy consumption per neuron block, which amounts to <inline-formula> <tex-math>$approx ~2.59$ </tex-math></inline-formula> pJ per neuron block and an overall energy budget of 663.66 pJ for the entire system considering the object recognition task.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"4115-4126"},"PeriodicalIF":5.2,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and Application of Brain-Inspired Circuit With Context-Dependent and State-Dependent Memory 情境依赖与状态依赖记忆的脑启发电路设计与应用

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-02 DOI: 10.1109/TCSI.2025.3554171

Gang Dou;Daoguo Li;Mei Guo;Herbert Ho-Ching Iu

{"title":"Design and Application of Brain-Inspired Circuit With Context-Dependent and State-Dependent Memory","authors":"Gang Dou;Daoguo Li;Mei Guo;Herbert Ho-Ching Iu","doi":"10.1109/TCSI.2025.3554171","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3554171","url":null,"abstract":"The context and the state of mind are important retrieval cues for long-term memory, which helps information to be retrieved quickly. However, most memristive circuits focus on the process of information memory, few studies consider the process of information retrieval. In this work, a brain-inspired circuit with context-dependent and state-dependent memory is proposed based on the three-level processing model of memory information, which integrates the processes of information memory and information retrieval. The circuit includes sensory memory module, short-term memory module, long-term memory module, information retrieval module, status module, and context module. In the circuit, information, contexts, and states are eventually transferred to long-term memory module for storage and retrieval. Meanwhile, the factors influencing information retrieval are considered, such as the degree of information memory, the time interval between information memory and retrieval, the context, and the state. And the proposed circuit has scalability, which realizes the memory of information in multiple contexts. Finally, based on the characteristics of memristors, the proposed circuit is extended for detecting damage to the machining accuracy of the mobile CNC lathe. Combining brain-inspired circuits with human memory mechanism, this work provides further reference for the research of brain-like intelligence.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2566-2577"},"PeriodicalIF":5.2,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hysteresis-Dependent Synchronized Load Shift Keying and Reconfigurable Class-D Power Amplifier-Based Fully Integrated Adaptive Control in Wireless Power Transfer System 基于滞后相关同步负载移位键控和可重构d类功率放大器的无线电力传输系统全集成自适应控制

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-02 DOI: 10.1109/TCSI.2025.3550479

Sayan Sarkar;Yuan Yao;Wing-Hung Ki;Chi-Ying Tsui

{"title":"Hysteresis-Dependent Synchronized Load Shift Keying and Reconfigurable Class-D Power Amplifier-Based Fully Integrated Adaptive Control in Wireless Power Transfer System","authors":"Sayan Sarkar;Yuan Yao;Wing-Hung Ki;Chi-Ying Tsui","doi":"10.1109/TCSI.2025.3550479","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3550479","url":null,"abstract":"A 13.56-MHz wireless power transfer (WPT) system with fully integrated transmitter (<inline-formula> <tex-math>${mathrm {T}}_{mathrm {X}}$ </tex-math></inline-formula>) and receiver (<inline-formula> <tex-math>${mathrm {R}}_{mathrm {X}}$ </tex-math></inline-formula>) chips is presented. The receiver’s output voltage is locally regulated using a linear current-sink-based regulator, while global power regulation is achieved at the transmitter through a hybrid control strategy that combines constant off-time and hysteretic control for a reconfigurable power amplifier. Synchronized load-shift keying at the receiver improves the relative change in the primary current of the transmitter by >15%. The adaptive digitally controlled active rectifier achieves a voltage conversion ratio (VCR) and power conversion efficiency (PCE) of 0.92 and 92.4%, respectively, for a <inline-formula> <tex-math>$200~Omega $ </tex-math></inline-formula> load resistance. The end-to-end efficiency is improved by 25% at heavy load and 14% at light load by enabling TX global power regulation. Both TX and RX chips were fabricated in the BCDlite 180 nm process with 1.8 V/5 V devices. This system achieves a greater operating distance, higher output power, and faster load-transient response while significantly reducing circuit and system design complexity.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2061-2074"},"PeriodicalIF":5.2,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multilogic Sense Amplifier With a Circuit for Dynamic Reference Voltage Generation 带有动态参考电压产生电路的多逻辑感测放大器

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-02 DOI: 10.1109/TCSI.2025.3554533

Yen-Jen Chang;Kun-Lin Tsai;Chun Cheng;Xu-Yao Chen

{"title":"Multilogic Sense Amplifier With a Circuit for Dynamic Reference Voltage Generation","authors":"Yen-Jen Chang;Kun-Lin Tsai;Chun Cheng;Xu-Yao Chen","doi":"10.1109/TCSI.2025.3554533","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3554533","url":null,"abstract":"The rapid development of artificial intelligence (AI) systems has engendered a considerable increase in the computational power required in data-intensive applications, including facial recognition and image processing applications. The conventional von Neumann architecture, in which large quantities of data are transmitted between processing units and memory units, creates a bottleneck in AI applications. In-memory computing (IMC) offers an efficient solution to this problem by enabling computations within memory units, thus reducing the need for data transmission. This paper proposes a multilogic sense amplifier (MSA) with a dynamic reference voltage (DRV) generation circuit (hereafter denoted as MSA-DRV) to enhance the performance and reduce the power consumption of static random-access memory (SRAM)-based IMC. The proposed MSA-DRV performs six logic operations, namely the AND, NAND, OR, NOR, XOR, and XNOR operations, within an SRAM array by using a novel DRV circuit. The DRV circuit enables the voltage threshold to be adaptively changed according to the requirements of different operations. Experimental results indicated that the proposed MSA-DRV had lower computational latency (on average 29.9% lower) and power consumption (on average 30.6% lower) than did a conventional sense amplifier design and reconfigurable assist sense amplifier. Thus, the proposed design can overcome the von Neumann bottleneck to facilitate high-speed, energy-efficient data processing, which is crucial for AI-based and other data-intensive applications.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"4052-4063"},"PeriodicalIF":5.2,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Super-Regenerative Reception Technique Based on an Improved General Theory in Linear Mode 基于改进广义理论的线性模式超再生接收技术

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-01 DOI: 10.1109/TCSI.2025.3552824

Junhong Liu;Guangyin Feng;Yi Wu;Fanyi Meng;Xiuyin Zhang

{"title":"Super-Regenerative Reception Technique Based on an Improved General Theory in Linear Mode","authors":"Junhong Liu;Guangyin Feng;Yi Wu;Fanyi Meng;Xiuyin Zhang","doi":"10.1109/TCSI.2025.3552824","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3552824","url":null,"abstract":"Super-regenerative receivers (SRRs) hold great promise as a low-cost solution for wireless communication due to their low power and relative simplicity. However, previous researches have primarily concentrated on super-regenerative amplifiers/oscillators, leading to limited insights into SRRs with inappropriate assumptions or dispensable operations, such as synchronous quench and baseband oversampling. This paper presents an improved general theory of super-regenerative reception in the linear mode that provides more design insights for digital communication. By analyzing the time-domain model of a general super-regenerative circuit, we derived a comprehensive frequency-domain model based on a convolution method, through which a concept of signal-lobe transfer function is introduced. Based on the proposed model, the effects of quench jitter and residual phenomenon are analyzed. Furthermore, an asynchronous quench method is introduced, which eliminates the requirement of synchronization between the modulated symbol and the quench signal, thus reducing the system complexity. To eliminate the baseband oversampling, especially for high-speed communications, main-lobe filtering and sub-sampling techniques are also proposed. To verify this general theory and proposed techniques, two SRRs with main-lobe filtering and sub-sampling were designed with ideal components and simulated using Cadence Virtuoso. The simulation results of two SRRs match with the proposed model very well. Overall, this paper provides a comprehensive analysis of super-regenerative reception for digital communication and offers valuable insights into its potentials and limitations.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2578-2591"},"PeriodicalIF":5.2,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Compact 321–343-GHz Integrated CMOS Radiator by Co-Designing Ring Oscillator and Multifunctional Antenna 环形振荡器与多功能天线协同设计的321 - 343 ghz小型集成CMOS散热器

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-01 DOI: 10.1109/TCSI.2025.3554680

Jiawei Yang;Yizhu Shen;Zhenghuan Wei;Sanming Hu

{"title":"A Compact 321–343-GHz Integrated CMOS Radiator by Co-Designing Ring Oscillator and Multifunctional Antenna","authors":"Jiawei Yang;Yizhu Shen;Zhenghuan Wei;Sanming Hu","doi":"10.1109/TCSI.2025.3554680","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3554680","url":null,"abstract":"This work presents a compact integrated CMOS radiator with a tuning range of 321-343 GHz. The miniaturization and enhanced performance of the radiator is achieved through co-designing a ring oscillator and a multifunctional antenna. The multi-stage ring oscillator features a variable common-source (CS) stage, which is proposed to achieve a broad frequency tuning range. To enhance the performance of the proposed variable CS stage for terahertz (THz) oscillator, wideband load impedances for all harmonics are theoretically analyzed and recursively optimized. The multifunctional antenna integrates six key functions into a simple compact structure: 1) inherently embedding the ring oscillator within a symmetric layout to ensure uniform operation, 2) directly combining the desired third harmonic signals without bulky and lossy passive networks, 3) radiating the desired third harmonic, 4) suppressing unwanted even harmonics, 5) providing fundamental inductance for the ring oscillator, and 6) supplying DC bias at virtual ground. For experimental validation, a THz radiator including a four-stage ring oscillator and a multifunctional antenna, is co-designed and fabricated in 40 nm CMOS process. The total chip area is as compact as 0.12 mm<inline-formula> <tex-math>${}^{mathbf {2}}$ </tex-math></inline-formula>. The measured output power and EIRP are −3.6 dBm and −9 dBm at 343 GHz, respectively, with a low DC power consumption of 46 mW. Moreover, the CMOS THz radiator is with a measured frequency tuning range of 6.7%, and DC-to-<inline-formula> <tex-math>$P_{mathbf {out}}$ </tex-math></inline-formula> efficiency of 0.95%. This compact radiator demonstrates promising potential for wideband and high-efficiency THz applications.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2603-2613"},"PeriodicalIF":5.2,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Real-Time 5.7–5.8 GHz 32-Beam Approximate Discrete Fourier Transform Spectrum Sensor for RF Perception on Xilinx Sx475T 基于Xilinx Sx475T的实时5.7-5.8 GHz 32波束近似离散傅立叶变换频谱传感器

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-01 DOI: 10.1109/TCSI.2025.3554078

Arjuna Madanayake;Umesha Kumarasiri;Sivakumar Sivasankar;Keththura Lawrance;Buddhipriya Gayanath;Hiruni Silva;Soumyajit Mandal;Renato J. Cintra

{"title":"Real-Time 5.7–5.8 GHz 32-Beam Approximate Discrete Fourier Transform Spectrum Sensor for RF Perception on Xilinx Sx475T","authors":"Arjuna Madanayake;Umesha Kumarasiri;Sivakumar Sivasankar;Keththura Lawrance;Buddhipriya Gayanath;Hiruni Silva;Soumyajit Mandal;Renato J. Cintra","doi":"10.1109/TCSI.2025.3554078","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3554078","url":null,"abstract":"The radio spectrum in the sub-6 GHz (FR1) band is crowded and contested, and is sought after by commercial, scientific and defense users. Situational awareness through spectrum sensing, and AI/ML-enabled perception that recognizes behaviors, patterns, modulations, devices and waveforms is a crucial need for emerging autonomous/cognitive radio systems. This work describes measurable progress in the use of extremely low complexity approximate DFT algorithms as multi-beam beamformers in the digital domain for multibeam spatial RF beamforming. The paper begins with a longterm vision for intelligent spectrum awareness across wide bands and multi-directions with multi-chiplet system in package hardware acceleration of both beamforming, Fourier and AI/ML algorithms, followed by a focus account of specific progress with digital architectures and real-time prototype implementations across the 5.7–5.8 GHz band for 32 RF beams. A real-time temporal frequency resolution of 100 kHz across 100 MHz of baseband bandwidth is achieved, across 32 simultaneous fully-digital RF-beams, using a Xilinx Sx475 FPGA implementation. Details of multiplierless approximate DFT beamformers, automated modulation recognition algorithms using AI/ML, analog channelization, spectrum sensing and perception architectures are also discussed. Over-the-air experiments using the RadioML.2018.a dataset confirmed both single source accuracy (better than 97%) and impact of multi-beams on AI/ML performance for multiple strong RFI sources.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"3777-3790"},"PeriodicalIF":5.2,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Bursting Oscillations Induced by the Variable Discontinuous Boundary in Chua’s Circuit 蔡氏电路中可变不连续边界引起的爆破振荡

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-03-31 DOI: 10.1109/TCSI.2025.3553484

Wenjie Zuo;Yi Zhang;Jin Song;Yuxun Zhu;Zhengdi Zhang

{"title":"Bursting Oscillations Induced by the Variable Discontinuous Boundary in Chua’s Circuit","authors":"Wenjie Zuo;Yi Zhang;Jin Song;Yuxun Zhu;Zhengdi Zhang","doi":"10.1109/TCSI.2025.3553484","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3553484","url":null,"abstract":"Bursting oscillations and bifurcation mechanisms in piecewise circuit systems have long been a research focus in the fields of dynamics and control. While most previous studies have focused on systems with a fixed discontinuous boundary, this paper examines systems with a variable discontinuous boundary. We develop a mathematical model based on Chua’s circuit and present numerical simulations of bursting oscillations under varying parameters. The impact of the translation of the discontinuous boundary (TDB) on the system’s topological structure and non-smooth bifurcations is analyzed. By combining the two-parameter bifurcation set of equilibrium points with the superposition diagram of the transformed phase diagram (TPD), we reveal mechanisms behind different bursting modes induced by the TDB. A Multisim-based simulation circuit is designed to validate the research results. It is found that the topology of the equilibrium branches of each subsystem remains the same during the TDB, but the number of smooth bifurcations changes due to the switching between subsystems. The TDB also alters the characteristics of the boundary equilibrium point, leading to the catastrophic disappearance or emergence of non-smooth limit cycles, which consequently changes the number of spiking oscillations. Moreover, the interaction of the slow passage effect (SPE) and the TDB causes the trajectory to remain in a delayed segment, affecting the number of spiking oscillations per period. Additionally, the TDB may lead to the disappearance of bursting oscillations, then the system exhibits a behavior similar to that of simple harmonic motion. Our study expands the scope of research on piecewise-smooth circuit systems.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2768-2777"},"PeriodicalIF":5.2,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and Analysis of a 28 GHz Bandwidth DC Coupled Active Balun With Phase-Amplitude Compensation in 40-nm CMOS 40纳米CMOS中带相位幅度补偿的28 GHz带宽直流耦合有源平衡轮设计与分析

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-03-31 DOI: 10.1109/TCSI.2025.3552956

Berke Gungor;Patrick Reynaert

引用次数: 0

Robust Fuzzy Control of Network-Type Re-Entrant Manufacturing Systems With Communication Delays 具有通信延迟的网络型可重入制造系统的鲁棒模糊控制

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-03-30 DOI: 10.1109/TCSI.2025.3570294

Yige Guo;Qing Gao;Maciej Ogorzałek;Jianbin Qiu;Jinhu Lü

引用次数: 0