IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

{"title":"Rethinking the Designing of Convolution Engine for Reconfigurable CNN Accelerator Using Sparse-Based Design Scheme","authors":"Yishuo Meng;Jianfei Wang;Siwei Xiang;Jia Hou;Zhijie Lin;Kuizhi Mei;Chen Yang","doi":"10.1109/TCSI.2025.3554332","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3554332","url":null,"abstract":"Convolutional neural networks (CNNs) are evolving as they are applied to more diverse environments and more difficult challenges. The evolving induces various convolution modes (e.g., <inline-formula> <tex-math>$1times 1$ </tex-math></inline-formula> convolution, 2-stride convolution and rectangle convolution) in current CNNs and makes it difficult for the hardware accelerators to efficiently support such various convolution modes. In this paper, it is found that an important difference of these convolution modes is the computation density. Therefore, the above convolution modes are regarded as structured sparse and claims that sparse-based design methodology can be applied for the implementation of the reconfigurable CNN accelerator. Subsequently, two critical architectural parameters, including input tile size and convolution engine (CE) scale, are evaluated based on Standard deviation of calculations (SDC), unsupported convolution mode (UCM) and unsuitable I FM size (UIS), DSP utilization ratio (DUR) as well as hardware resource overhead (HRO), respectively. With the aid of the optimal parameters, a high-parallelism and flexible CE array and a high-performance and reconfigurable CNN architecture are designed. The accelerator was implemented on a Xilinx VC709 FPGA and ran at a clock frequency of 300 MHz, achieving 921.60 to 1382.40 GOPS while supporting various convolution modes. Compared with previous dense-/sparse-based works, the proposed accelerator can realize <inline-formula> <tex-math>$1.35times $ </tex-math></inline-formula> to <inline-formula> <tex-math>$10.77times $ </tex-math></inline-formula> improvements on performance and <inline-formula> <tex-math>$1.22times $ </tex-math></inline-formula> to <inline-formula> <tex-math>$2.84times $ </tex-math></inline-formula> improvements on DSP efficiency while deploying VGG16.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"3983-3996"},"PeriodicalIF":5.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Four-Port Probe Calibration Using 64-Term Error Model for On-Wafer S-Parameter Measurement of Microwave Circuits Up to 110 GHz","authors":"Jiefeng Zhou;Ling Zhang;Ziyang Chen;Da Li;Jun Fan;Er-Ping Li","doi":"10.1109/TCSI.2025.3544672","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3544672","url":null,"abstract":"This article presents a novel four-port probe calibration method for on-wafer S-parameter measurement of microwave circuits and, for the first time, realizes measurement verification up to 110 GHz. The method regards the 64 error terms in the four-port probe calibration as an error matrix, which can be solved by a homogeneous equation system using a generalized scatter matrix theory. The calibration algorithm can consider the crosstalk between the probes and improve the calibration accuracy at high frequencies. This method only requires six calibration standards to complete the four-port probe calibration. Only one coupled differential line with a symmetric structure is needed as the Thru, which replaces the traditional U-shape and asymmetric Thru and effectively reduces the number of calibration standards used in the four-port probe calibration. In addition, the method combined with an optimization method accurately and efficiently calculates the parasitic parameters of the calibration standards at high frequencies. The proposed method is validated by three different devices under test (DUTs) up to 110 GHz. Their S-parameters obtained by the proposed method, including all the pure-mode and mode-conversion terms, have high accuracy in magnitude and phase, proving the correctness and convenience of this method.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 10","pages":"5471-5481"},"PeriodicalIF":5.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Fully-Integrated Many-Electrodes Pulsed-Voltage Control Architecture for Arbitrary-Waveform Neural Stimulation With High Energy Efficiency","authors":"Sergio Massaioli;Marco F. Carlino;Georges G. E. Gielen","doi":"10.1109/TCSI.2025.3555895","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3555895","url":null,"abstract":"Deeply implantable neural stimulation calls for architectural solutions that are small, efficient and flexible, and that can stimulate many electrodes. To this end, this paper proposes the use of a pulsed (chopped) voltage stimulator, implemented using a low-complexity switch network with fully adaptive real-time control. The fully-integrated control architecture guarantees current waveform reconstruction and charge balancing by continuously monitoring the charge delivered to the electrode, thus offering robustness towards power-supply voltage and electrode impedance variations. The architecture has a high energy efficiency across the entire output operating range. The output waveform is generated in charge samples (slices) of controlled amount; by controlling these slices properly, the desired arbitrary stimulation waveform is constructed. A voltage monitoring circuit is used to apply active charge balancing; the duration of the balancing phase is adjusted by varying the number of charge samples. The feasibility of the architecture is demonstrated with a chip prototype manufactured in a 180 nm, 1.8 V/5 V CMOS process, and has an area of only 0.027 mm2 per non-multiplexed stimulator channel. Across the entire output operating range, the experimental validation of the prototype demonstrates a source energy efficiency that is up to <inline-formula> <tex-math>$35,%$ </tex-math></inline-formula> better than previously published implementations. The results show that this architecture is a viable solution for next-generation systems for neuromodulation and closed-loop neural monitoring.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 10","pages":"5447-5456"},"PeriodicalIF":5.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Rational-Exponent Filters with Applications to Generalized Exponent Filters","authors":"Samiya A. Alkhairy","doi":"10.1109/TCSI.2025.3545459","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3545459","url":null,"abstract":"We present filters with rational exponents in order to provide a continuum of filter behavior not classically achievable. We discuss their stability, the flexibility they afford, and various representations useful for analysis, design and implementations. We do this for a generalization of second-order filters which we refer to as rational-exponent Generalized Exponent Filters (GEFs) that are useful for a diverse array of applications. We present equivalent representations for rational-exponent GEFs in the time and frequency domains: transfer functions, impulse responses, and integral expressions - the last of which allows for efficient real-time processing without preprocessing requirements. Rational-exponent filters enable filter characteristics to be on a continuum rather than limiting them to discrete values thereby resulting in greater flexibility in the behavior of these filters without additional complexity in causality and stability analyses compared with classical filters. In the case of GEFs, this allows for having arbitrary continuous rather than discrete values for filter characteristics such as 1) the ratio of 3dB quality factor to maximum group delay - particularly important for filterbanks which have simultaneous requirements on frequency selectivity and synchronization; and 2) the ratio of 3dB to 15dB quality factors that dictates the shape of the frequency response magnitude.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2139-2152"},"PeriodicalIF":5.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Observability Verification System Analysis for Observability and Reconstructibility of Probabilistic Logical Control Networks","authors":"Yalu Li;Haitao Li;Gaoxi Xiao","doi":"10.1109/TCSI.2025.3553463","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3553463","url":null,"abstract":"Observability and reconstructibility are two fundamental issues in modern control theory, which are important in both state estimation and observer design. The existing results for verifying the observability and reconstructibility of probabilistic logical control networks (PLCNs) have exponential complexities. This article presents a new approach to verify the observability and reconstructibility of PLCNs, which can greatly reduce the computational complexity. Specifically, the problem is tackled in three different steps. Firstly, based on the division of the state pair space, an observability verification system is established. Secondly, the equivalence between the stabilization of the proposed observability verification system and the observability of PLCNs is revealed, and a new criterion is established to solve the observability of PLCNs. Under the framework, the computational complexity is discussed. Thirdly, the relationship between observability and reconstructibility of PLCNs is unveiled, and some new criteria are established to solve two kinds of reconstructibility problems for PLCNs. Finally, an example of a biological network, apoptosis network, is presented to demonstrate the feasibility of the methods proposed in this article.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"4273-4283"},"PeriodicalIF":5.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Generalized Discrete-Time Variable Gain ADRC for Nonlinear Systems and Its Application to Parallel Teleoperated Manipulators","authors":"Shaomeng Gu;Jinhui Zhang;Long Cheng;Yuanqing Wu","doi":"10.1109/TCSI.2025.3555204","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3555204","url":null,"abstract":"In this paper, we propose a novel generalized discrete-time variable gain active disturbance rejection control (DTVGADRC) method for the <italic>n</i>-th order discrete-time nonlinear systems. The error-driven generalized DTVGADRC can dynamically improve the control performances, including generalized discrete-time variable gain tracking differentiator (DTVGTD), generalized discrete-time variable gain extended state observer (DTVGESO), and generalized discrete-time variable gain controller (DTVGC). Furthermore, the stability analysis of generalized DTVGADRC is performed, and the parameters in the variable gain functions are determined by the theoretical analysis. Finally, the generalized DTVGADRC method is applied to parallel teleoperated manipulators, and the experiment results are presented to illustrate effectiveness of the proposed method.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2868-2877"},"PeriodicalIF":5.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Efficient Multi-View Cross-Attention Accelerator for Vision-Centric 3D Perception in Autonomous Driving","authors":"Dongxu Lyu;Zhenyu Li;Yansong Xu;Gang Wang;Wenjie Li;Yuzhou Chen;Liyan Chen;Weifeng He;Guanghui He","doi":"10.1109/TCSI.2025.3555837","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3555837","url":null,"abstract":"Vision-centric 3D perception has become a key mechanism in autonomous driving. It achieves exceptional perceptual performance mainly by introducing a novel attention, multi-view cross-attention (MVCA), for learnable feature extraction and fusion from surround-view cameras. Despite its superiority, MVCA encounters severe inefficiencies in sample, processing elements (PE), and pipelined processing, owing to the redundant and non-uniform sampling-aggregation and rigorous inter-operator dependencies. To address these issues, this article proposes a dedicated MVCA accelerator, MVAtor, with algorithm-architecture co-optimization for vision-centric 3D perception based on multi-view inputs flexibly. For sample inefficiency, a 3-tier hybrid static-dynamic sample and a sensitivity-aware feature pruning approach are proposed to eliminate the 86.03% sample overhead and 24.48% memory requirement, only incuring <1%> <tex-math>$53.7sim 96.1$ </tex-math></inline-formula>% energy-delay product reduction. For pipeline inefficiency, a fine-grained-tiling assisted highly-pipelined architecture is constructed in MVAtor by exploiting the decoupling opportunities on inter-view sparsity, thereby saving 61.03% external memory access while boosting the overall throughputs by <inline-formula> <tex-math>$1.83times $ </tex-math></inline-formula>. Extensively evaluated on representative benchmarks, MVAtor attains <inline-formula> <tex-math>$1.38sim 7.67times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$1.67sim 11.15times $ </tex-math></inline-formula> improvement on energy and area efficiency respectively, compared to the state-of-the-art related accelerators.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 7","pages":"3272-3285"},"PeriodicalIF":5.2,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144550359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 7.2–29.8 GHz LNA With 1.35–2.67-dB NF Using Coupled-Line-Based Transformers in 0.15- μm GaN-on-SiC Technology","authors":"Cheng-Jie Hu;Hui-Yang Li;Jin-Xu Xu;Li Gao;Xiu Yin Zhang","doi":"10.1109/TCSI.2025.3554211","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3554211","url":null,"abstract":"This paper presents a broadband low-noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) in 0.15-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m GaN-on-SiC technology. The LNA circuit is designed into a three-stage topology with three coupled-line structures. The first coupled-line structure is designed at the first stage for wideband input impedance matching and noise cancellation, while the second one is employed at the inter-stage to realize the <inline-formula> <tex-math>$g_{m}$ </tex-math></inline-formula>-boost for gain enhancement. Then, the last coupled-line structure forms a positive feedback signal paths from the drain to the gate of the output-stage transistor, which compensates the gain degradation at the high frequency band. With these three coupled-line structures, flat gain performance and low noise figure are achieved in a broadband frequency range. For demonstration, the LNA MMIC is fabricated. The measured results show a maximum gain of 22.6 dB at 27.6 GHz and a 3-dB bandwidth of 22.6 GHz from 7.2 to 29.8 GHz. The in-band noise figure is measured as 1.35-2.67 dB, while the output 1dB gain compression point (OP1dB) and output third-order intercept point (OIP3) are 20.9 dBm and 34.8 dBm at 28.5 GHz, respectively. The fabricated LNA has a compact die area of 2.64 mm2 including all test pads.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 10","pages":"5302-5313"},"PeriodicalIF":5.2,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Adaptive Beam-Steering dToF LiDAR System Using Addressable Multi-Channel VCSEL Transmitter, 128 × 80 SPAD Sensor, and ML-Based Edge-Computing Object Detection","authors":"Yifan Wu;Miao Sun;Sifan Zhou;Tao Xia;Lei Wang;Jier Wang;Yuan Li;Ming Zhong;Rui Bai;Xuefeng Chen;Yuanjin Zheng;Patrick Yin Chiang;Shenglong Zhuo;Lei Qiu","doi":"10.1109/TCSI.2025.3550450","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3550450","url":null,"abstract":"In this work, a solid-state direct time-of-flight (dToF) and adaptive beam-steering Light Detection and Ranging (LiDAR) system is proposed for machine learning (ML) based object detection. To leverage the capabilities of software and hardware, a co-optimization design from a neural network based algorithm to the architecture of transmitter, receiver and optical components is realized. Firstly, an object detection neural network is proposed for the depth-only input algorithm, which indicates the Region of Interest (ROI) in the illuminating field and gives hints of opened scan channels in the next two frames to decrease the total cost of the laser driver and sensor array. Next, the proposed network utilizes the Cross-Stage-Patrial (CSP) block to replace the residual structure in the backbone to achieve a lightweight performance and is implemented on the NVIDIA-Jetson to verify the system-level adaptive beam steering feature. To realize the smart working mode, a customized multi-channel and addressable TX is designed for adaptive and optical control to save power consumption and extend the ranging distance. At the same time, a <inline-formula> <tex-math>$128times 80$ </tex-math></inline-formula> resolution RX which consists of Single-Photon Avalanche Diodes (SPADs) and column-wise Time-to-Digital Converter (TDC) is incorporated to capture the returned photons for combining sub-regions into an entire depth map. Next, to customize the specific scanning mechanism, for the optical setup, a cylindrical lens array is designed to reshape the laser beam, which matches the pattern of the transmitter to illuminate different targeted objects. Both the laser driver chip and the sensor chip with a <inline-formula> <tex-math>$128times 80$ </tex-math></inline-formula> SPAD array are fabricated in the 180-nm Bipolar-CMOS-DMOS (BCD) process. Finally, the laser driver chip realizes the power of 5 W with an adjustable pulse width of 1.5 ns and the SPAD array integrates the depth accuracy of 5 cm at 15 m. Due to that the neural network realizes an accuracy up to 0.8, a low-power solid-state LiDAR prototype with adaptive beam steering is demonstrated.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2089-2102"},"PeriodicalIF":5.2,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"MINA: A Hardware-Efficient and Flexible Mini-InceptionNet Accelerator for ECG Classification in Wearable Devices","authors":"Hoai Luan Pham;Thi Diem Tran;Vu Trung Duong Le;Yasuhiko Nakashima","doi":"10.1109/TCSI.2025.3553837","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3553837","url":null,"abstract":"Classification is a crucial aspect of cardiovascular-related challenges, requiring thorough research and optimization to develop effective solutions for both patients and doctors. Recently, rapid advancements in artificial intelligence, particularly Convolutional Neural Networks (CNNs), have introduced numerous effective methods, significantly improving disease classification in Electrocardiogram (ECG) analysis. However, existing CNN-based accelerators often encounter challenges such as high parameter counts, limited flexibility in handling diverse CNN configurations, and inefficient hardware utilization. To address these issues, this paper proposes the Mini InceptionNet Accelerator (MINA), a hardware-efficient and flexible accelerator designed specifically for one-dimensional (1-D) CNN-based ECG classification. First, a novel 1-D CNN model, Mini InceptionNet, reduces the parameter count by 41.6% compared to the smallest existing 1-D CNN, minimizing memory requirements while maintaining high classification accuracy. Second, a flexible Processing Element Array (PEA) is designed with a Sharing Buffer Allocator (SBA) to support dynamic data coordination across various network topology parameters. Third, each Processing Element (PE) is equipped with four Local Data Memories (LDMs) and an ALU, enabling efficient intermediate data storage and versatile operations for modern CNN models. To demonstrate its effectiveness, MINA has been successfully implemented and verified on the ZCU102 FPGA at the system-on-chip level. FPGA evaluations show that MINA achieves <inline-formula> <tex-math>$1.3times - 2.9times $ </tex-math></inline-formula> higher energy efficiency (<italic>GOP/s/MeLUT</i>) than state-of-the-art 2-D CNN accelerators. Compared to existing 1-D CNN accelerators, MINA achieves at least <inline-formula> <tex-math>$1.53times $ </tex-math></inline-formula> improvement in the area-delay product (ADP). Additionally, weight pruning is discussed as a supporting strategy, achieving up to <inline-formula> <tex-math>$3times $ </tex-math></inline-formula> faster inference time and a <inline-formula> <tex-math>$2.13times $ </tex-math></inline-formula> improvement in ADP at 70% sparsity.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2740-2753"},"PeriodicalIF":5.2,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}