IEEE Transactions on Circuits and Systems I: Regular Papers最新文献_第7页

Adaptive Low-Order Harmonic Currents Suppression in AC Power System Using Fractional-Order Circuit 利用分数阶电路抑制交流电力系统中的自适应低阶谐波电流

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-29 DOI: 10.1109/TCSI.2024.3444005

Zhile Lin;Liangzong He;Hongyan Zhou

{"title":"Adaptive Low-Order Harmonic Currents Suppression in AC Power System Using Fractional-Order Circuit","authors":"Zhile Lin;Liangzong He;Hongyan Zhou","doi":"10.1109/TCSI.2024.3444005","DOIUrl":"10.1109/TCSI.2024.3444005","url":null,"abstract":"This paper proposed an innovative fractional-order circuit LC (FOC-LC) based resonant filtering method to suppress low-order harmonic currents in AC power system. By constructing the FOC-LC harmonic suppression branch and applying a corresponding modulation strategy, the impedance complex plane maintains symmetrical resonance inductance and capacitance. This leads to an extremely low equivalent impedance for different harmonic currents, effectively suppressing harmonics with diverse frequencies and magnitudes. The proposed method demonstrates robustness to device parameters and maintains reliable harmonic suppression performance within an acceptable error range. The utilization of fractional-order circuits allows for auxiliary charging, modifying output port capacitance, adjusting equivalent resistance, and even achieving negative resistance characteristics. This results in minimal resonance equivalent resistance in the harmonic suppression branch. To verify feasibility, a 1.2 kW prototype was implemented, yielding promising results. The experimental validation validates the practical applicability and effectiveness of this method.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4446-4457"},"PeriodicalIF":5.2,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Duty-Cycle-Error-Immune Reference Frequency Doubling Technique for Fractional-N Digital PLLs 用于分数-N$ 数字 PLL 的占空比-误差-免疫参考频率倍增技术

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-28 DOI: 10.1109/TCSI.2024.3439210

Amr I. Eissa;Enrique Alvarez-Fontecilla;Colin Weltin-Wu;Ian Galton

{"title":"A Duty-Cycle-Error-Immune Reference Frequency Doubling Technique for Fractional-N Digital PLLs","authors":"Amr I. Eissa;Enrique Alvarez-Fontecilla;Colin Weltin-Wu;Ian Galton","doi":"10.1109/TCSI.2024.3439210","DOIUrl":"10.1109/TCSI.2024.3439210","url":null,"abstract":"Increasing a PLL’s reference frequency offers significant performance advantages, but doing so by increasing the PLL’s crystal oscillator frequency is not a viable option in many applications. Instead, a frequency doubler can be used to derive a reference signal with twice the frequency of the crystal oscillator, but conventional PLLs are highly sensitive to the crystal oscillator’s duty cycle error in such cases. Prior solutions to this problem involve calibration techniques which impose convergence speed versus accuracy tradeoffs. In contrast, this paper proposes a system modification which makes a PLL immune to such duty cycle errors without the need for calibration. The technique is presented and analyzed in the context of a delta-sigma frequency-to-digital converter (\u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000-FDC) based PLL. Analysis and behavioral simulations with nonideal circuit parameters show that the worst-case convergence time is at least 10 times faster than that of the prior techniques. Additionally, the proposed \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000-FDC includes other modifications which improve its performance relative to comparable prior \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000-FDCs.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4524-4537"},"PeriodicalIF":5.2,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information IEEE 电路与系统论文集--I：常规论文出版信息

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-28 DOI: 10.1109/TCSI.2024.3441434

引用次数: 0

A Nonlinear Stream Cipher for Encryption of Test Patterns in Streaming Scan Networks 用于流扫描网络中测试模式加密的非线性流密码

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-28 DOI: 10.1109/tcsi.2024.3447080

Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Włodarczak

引用次数: 0

Analysis and Design of a 570-Stage CMOS RF-DC Rectifier With Ground Shielded Input Coupling Capacitors 带有接地屏蔽输入耦合电容器的 570 级 CMOS 射频-直流整流器的分析与设计

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-28 DOI: 10.1109/TCSI.2024.3447013

Yoomi Park;Sangjin Byun

{"title":"Analysis and Design of a 570-Stage CMOS RF-DC Rectifier With Ground Shielded Input Coupling Capacitors","authors":"Yoomi Park;Sangjin Byun","doi":"10.1109/TCSI.2024.3447013","DOIUrl":"10.1109/TCSI.2024.3447013","url":null,"abstract":"This paper presents an analysis and design of an 884-MHz, −41.8-dBm input power sensitivity, 570-stage CMOS RF-DC rectifier with ground shielded input coupling capacitors. First, we have presented the input impedance model of an N-stage CMOS RF-DC rectifier by applying \u0000<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>\u0000-Y transform to the input coupling capacitors and including a nonlinear input resistance of the MOS transistors. Based on the developed model, we have carried out the steady-state and transient analyses of the N-stage RF-DC rectifier. According to the analysis results, the input power sensitivity increases as the RF-DC rectifier contains more rectifier cells. However, integrating a large number of rectifier cells normally reduces the passive amplification gain of the matching network and thus may not bring the desired results. In this paper, we propose the RF-DC rectifier adopting a metal ground shield plane beneath the input coupling capacitors thereby incorporating as many as 570 rectifier cells without lowering the passive amplification gain. By doing so, the 884-MHz, 570-stage RF-DC rectifier implemented in a 28nm CMOS process achieves the measured input power sensitivity of −41.8dBm at 1V output DC voltage. The measured recharging time from 0.88V to 1.0V is 11.1 seconds when the storage capacitor is 1nF.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"5494-5505"},"PeriodicalIF":5.2,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Circuits and Systems Society Information 电气和电子工程师学会电路与系统协会信息

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-28 DOI: 10.1109/TCSI.2024.3441432

引用次数: 0

IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors IEEE 《电路与系统》期刊--I：常规论文作者须知

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-28 DOI: 10.1109/TCSI.2024.3441436

引用次数: 0

Bidirectional High Step-Up/Down DC/DC Converter With a Coupled Inductor and Switched Capacitor 采用耦合电感器和开关电容器的双向高升/降压 DC/DC 转换器

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-27 DOI: 10.1109/tcsi.2024.3436694

Sang-Wha Seo, Joon-Hyoung Ryu, June-Seok Lee

引用次数: 0

Efficient Integer-Only-Inference of Gradient Boosting Decision Trees on Low-Power Devices 低功耗设备上梯度提升决策树的高效整数推理

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-27 DOI: 10.1109/tcsi.2024.3446582

Majed Alsharari, Son T. Mai, Roger Woods, Carlos Reaño

引用次数: 0

Low-Power High Precision Floating-Point Divider With Bidimensional Linear Approximation 采用双维线性逼近的低功耗高精度浮点运算除法器

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-27 DOI: 10.1109/tcsi.2024.3447830

Gennaro Di Meo, Antonio Giuseppe Maria Strollo, Davide De Caro, Luca Tegazzini, Ettore Napoli

引用次数: 0