IEEE Transactions on Circuits and Systems I: Regular Papers最新文献_第7页

2024 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 71 2024索引IEEE电路与系统交易I：常规论文卷71

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-27 DOI: 10.1109/TCSI.2024.3521726

引用次数: 0

Cloud-Edge Model Predictive Control of Cyber-Physical Systems Under Cyber Attacks 网络攻击下网络物理系统的云边缘模型预测控制

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-27 DOI: 10.1109/TCSI.2024.3520598

Yaning Guo;Qi Sun;Yintao Wang;Quan Pan

引用次数: 0

A Wide Air Gap IPT System for Distribution Insulator Applications Based on Reconfigurable Autotransformer Coupling Structure 基于可重构自耦变压器耦合结构的配电绝缘子宽气隙IPT系统

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-24 DOI: 10.1109/TCSI.2024.3519728

Peng Gu;Yunrui Hao;Xingzhen Guo;Dongsheng Yang;Peng Zhao;Bowen Zhou;Yijie Wang

{"title":"A Wide Air Gap IPT System for Distribution Insulator Applications Based on Reconfigurable Autotransformer Coupling Structure","authors":"Peng Gu;Yunrui Hao;Xingzhen Guo;Dongsheng Yang;Peng Zhao;Bowen Zhou;Yijie Wang","doi":"10.1109/TCSI.2024.3519728","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3519728","url":null,"abstract":"In this paper, an inductive power transfer (IPT) system for distribution insulator based on reconfigurable autotransformer magnetic coupler (ATMC) is proposed. A three-stage IPT system architecture is proposed based on the form of a 35kV insulator structure. A novel multi-tap magnetic coupler in the form of autotransformer is proposed. The voltage conversion ratio and output characteristics of the IPT system can be reconstructed by changing the winding taps connected to the IPT system. An ATMC-based IPT system circuit model is established. The parameters of ATMC are optimized. The effect of system parameter reconstruction by changing the winding taps of ATMC is analyzed. An IPT system based on a reconfigurable ATMC with three winding taps on both the primary and secondary sides is designed, an experimental prototype is built. <inline-formula> <tex-math>$3times 3$ </tex-math></inline-formula> sets of experiments are completed, and the solution to reconstruct the system state by changing the winding taps of ATMC is verified. The maximum efficiency of the system is close to 90%.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"963-975"},"PeriodicalIF":5.2,"publicationDate":"2024-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Tsetlin Machine-Based Image Classification FPGA Accelerator With On-Device Training Tsetlin机器图像分类FPGA加速器与设备上训练

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-23 DOI: 10.1109/TCSI.2024.3519191

Svein Anders Tunheim;Lei Jiao;Rishad Shafik;Alex Yakovlev;Ole-Christoffer Granmo

{"title":"Tsetlin Machine-Based Image Classification FPGA Accelerator With On-Device Training","authors":"Svein Anders Tunheim;Lei Jiao;Rishad Shafik;Alex Yakovlev;Ole-Christoffer Granmo","doi":"10.1109/TCSI.2024.3519191","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3519191","url":null,"abstract":"The Tsetlin Machine (TM) is a novel machine learning algorithm that uses Tsetlin automata (TAs) to define propositional logic expressions (clauses) for classification. This paper describes a field-programmable gate array (FPGA) accelerator for image classification based on the Convolutional Coalesced Tsetlin Machine. The accelerator classifies booleanized images of <inline-formula> <tex-math>$28times 28$ </tex-math></inline-formula> pixels into 10 classes, and is configured with 128 clauses in a highly parallel architecture. To achieve fast clause evaluation and class prediction, the TA action signals and the clause weights per class are available from registers. Full on-device training is included, and the TAs are implemented with 34 Block RAM (BRAM) instances which operate in parallel. Each BRAM is addressed by the clause number and has a 72-bit word width that supports 8 TAs. The design is implemented in a Xilinx Zynq Ultrascale+ XCZU7 FPGA. Running at 50 MHz, the accelerator core achieves 134k image classifications per second, with an energy consumption per classification of <inline-formula> <tex-math>$13.3~mu $ </tex-math></inline-formula> J. A single training epoch of 60k samples requires a processing time of 1.5 seconds. The accelerator obtains a test accuracy of 97.6% on MNIST, 84.1% on Fashion-MNIST and 82.8% on Kuzushiji-MNIST.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"830-843"},"PeriodicalIF":5.2,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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HAST: A Hardware-Efficient Spatio-Temporal Correlation Near-Sensor Noise Filter for Dynamic Vision Sensors 用于动态视觉传感器的硬件高效时空相关近传感器噪声滤波器

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-23 DOI: 10.1109/TCSI.2024.3517133

Pradeep Kumar Gopalakrishnan;Chip-Hong Chang;Arindam Basu

{"title":"HAST: A Hardware-Efficient Spatio-Temporal Correlation Near-Sensor Noise Filter for Dynamic Vision Sensors","authors":"Pradeep Kumar Gopalakrishnan;Chip-Hong Chang;Arindam Basu","doi":"10.1109/TCSI.2024.3517133","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3517133","url":null,"abstract":"The Dynamic Vision Sensor (DVS) is a bio-inspired image sensor which has many advantages such as high dynamic range, high bandwidth, high temporal resolution and low power consumption for Internet of Video Things and Edge Computing applications. However, spuriously generated Background Activity (BA) noise events can significantly degrade the quality of DVS output and cause unnecessary computations throughout the image processing chain, reducing its energy efficiency. Near-sensor filters can mitigate this problem by preventing the BA noise events from reaching downstream stages. In this paper, we propose a novel, hardware-efficient, spatio-temporal correlation filter (HAST) for near-sensor BA noise filtering. It uses compact two-dimensional binary arrays along with simple, arithmetic-free hash-based functions for storage and retrieval operations. This approach eliminates the need to use timestamps for determining the chronological order of events. HAST uses much lower memory and energy compared to other hardware-friendly filters (BAF/STCF) while matching their performance in simulations with standard datasets; for a sensor of resolution <inline-formula> <tex-math>$346times 260$ </tex-math></inline-formula> pixels, it requires only 5–18% of their memory, and about 15% of their energy per event for correlation time <inline-formula> <tex-math>$tau $ </tex-math></inline-formula> ranging from 1 to 50 ms. The memory and energy gains of the filter increase with sensor resolution. In FPGA implementation, HAST achieves about 29% higher throughput than BAF/STCF while utilizing only about 5% of their memory. The filter parameter values can be chosen by Design Space Exploration (DSE) for optimized performance-resource trade-offs based on application requirements.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1332-1345"},"PeriodicalIF":5.2,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multiasynchronous Extended Dissipative Sliding Mode Control of LC Circuits in Grid-Connected System Under Actuator Attacks 执行器攻击下并网系统LC电路的多异步扩展耗散滑模控制

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-23 DOI: 10.1109/TCSI.2024.3517703

Junyi Wang;Ying Zheng;Jinliang Ding;Xiangpeng Xie;Wenjun Zhang

{"title":"Multiasynchronous Extended Dissipative Sliding Mode Control of LC Circuits in Grid-Connected System Under Actuator Attacks","authors":"Junyi Wang;Ying Zheng;Jinliang Ding;Xiangpeng Xie;Wenjun Zhang","doi":"10.1109/TCSI.2024.3517703","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3517703","url":null,"abstract":"This article investigates the event-triggered multiasynchronous dissipative sliding mode control problem for the gird-connected systems, where the coupled Inductance-Capacitance (LC) oscillators in electrical networks are subject to actuator attacks and external disturbances. To reduce the communication burden, the dynamic event-triggered mechanisms (DETMs) are introduced along with the switching mechanism for multiple topologies. Specifically, the topology switching process is further viewed as a general uncertain semi-Markov (GUSM) jumping process. This jumping process along with the DETM is thus represented by hidden Markov model (HMM). Then the distributed integral-type sliding mode controller is constructed on the top of the HMM. Sufficient conditions for the desired performance of the closed-loop synchronization error system are derived by constructing the mode-dependent Lyapunov-Krasovskii functional (LKF) with extended dissipativity analysis. The numerical simulation of LC oscillators in the single-phase photovoltagic grid interconnection process is conducted to validate the proposed method.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1609-1620"},"PeriodicalIF":5.2,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 40 nm Cryo-CMOS Homodyne-Demodulation Readout SoC for Superconducting Qubits 用于超导量子比特的40nm Cryo-CMOS同差解调读出SoC

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-20 DOI: 10.1109/TCSI.2024.3518472

Donggyu Minn;Kiseo Kang;Jaeho Lee;Seongchan Bae;Byungjun Kim;Jaehoon Lee;Jae-Yoon Sim

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FALSAx: An Integrated Framework for Accuracy and Logic Synthesis Estimation of Approximate Adders 近似加法器精度和逻辑综合估计的集成框架

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-19 DOI: 10.1109/TCSI.2024.3511383

Morgana Macedo Azevedo da Rosa;Leonardo Antonietti;Rodrigo Lopes;Eloisa Barros;Eduardo Antonio Ceśar da Costa;Rafael Soares

{"title":"FALSAx: An Integrated Framework for Accuracy and Logic Synthesis Estimation of Approximate Adders","authors":"Morgana Macedo Azevedo da Rosa;Leonardo Antonietti;Rodrigo Lopes;Eloisa Barros;Eduardo Antonio Ceśar da Costa;Rafael Soares","doi":"10.1109/TCSI.2024.3511383","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3511383","url":null,"abstract":"This work proposes an integrated framework for accuracy and logic synthesis (LS) estimation of approximate adders (FALSAx). It represents a versatile and robust framework designed to estimate the accuracy, power, and area of various approximate adders (AxAs) for any input width (W) and K bits of approximation using machine learning (ML) models. FALSAx facilitates performance predictions and optimization for different AxAs configurations through meticulously curated datasets and ML-driven analysis. The framework’s capability to automatically generate Pareto fronts from estimated values aids in identifying optimal trade-offs among crucial metrics, providing essential insights for circuit design and optimization. The FALSAx includes four internal frameworks: FrAQ, PILSE, and FELSE, which estimates dynamic power, total leakage power, and area, with frequency variations automatically, and the FALED dataset of the FALSAx. As a case study, this work analyzed 16 types of AxAs on FALSAx: AMA-V, AxPPA, COPY, TRUNC, ETA, LOA, HOERAA, LDCA, LZTA, HEAA, M-HEAA, HERLOA, M-HERLOA, HOAANED, OLOCA, and SETA. The rigorous analysis provided by FALSAx revealed that HERLOA, M-HERLOA, M-HEAA, and AxPPA demonstrated superior accuracy metrics such as SSIM, NCC, MAE, and MRE. Furthermore, power analysis showed that AxPPA exhibited the best power efficiency for lower approximation bits (<inline-formula> <tex-math>$K leq 3$ </tex-math></inline-formula>). At the same time, gate-free adders like COPY, TRUNC, AMA-V, LDCA, and LZTA were more power-efficient for higher approximation bits (<inline-formula> <tex-math>$K gt 3$ </tex-math></inline-formula>). Area estimations indicated that AxPPA maintained competitive efficiency for lower approximation bits (<inline-formula> <tex-math>$K leq 5$ </tex-math></inline-formula>), while TRUNC and LDCA were more efficient for higher bits (<inline-formula> <tex-math>$K gt 5$ </tex-math></inline-formula>).","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1679-1692"},"PeriodicalIF":5.2,"publicationDate":"2024-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A −79 dBm 7.56 nW 433 MHz Wake-Up Receiver With Interference Suppression for IoT Application −79 dBm 7.56 nW 433 MHz具有干扰抑制的唤醒接收器，用于物联网应用

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-19 DOI: 10.1109/TCSI.2024.3518462

Jianhang Yang;Rong Zhou;Xianlong Xiong;Linwei Wang;Hongjian Lan;Shubin Liu;Zhangming Zhu

{"title":"A −79 dBm 7.56 nW 433 MHz Wake-Up Receiver With Interference Suppression for IoT Application","authors":"Jianhang Yang;Rong Zhou;Xianlong Xiong;Linwei Wang;Hongjian Lan;Shubin Liu;Zhangming Zhu","doi":"10.1109/TCSI.2024.3518462","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3518462","url":null,"abstract":"In this paper, we present an ultra-low power wake-up receiver (WuRX) with effective interference suppression capability. A specific robust design has been implemented to address the common interference issues in the industrial, scientific, and medical (ISM) frequency band. A mathematical expression is derived in this paper for the minimum signal-to-noise ratio (SNR) required by the comparator at which a envelope detector first (ED-first) WuRX can detect the wake-up message in the presence of interference. Aiming to meet the minimum SNR requirements, a quasi-direct coupling (QDC) baseband buffer scheme is proposed. Compared to the output SNR of traditional AC schemes, the QDC baseband buffer scheme achieves a 4.16 dB increase in output SNR under optimal conditions. To solve the problem where traditional comparator calibration schemes require recovery time after sudden disappearance of interference, the multipath signal detection (MPSD) scheme proposed in this paper can immediately detect information following the disappearance of interference, which improves detection efficiency. The WuRX is manufactured in 65nm LP process, consuming 7.56nW at a 0.4V power supply, with a sensitivity of −79dBm in the 433MHz ISM band. Under continuous wave (CW) interference, the receiver achieves a signal-to-interference ratio (SIR) of −31dB at a frequency offset of 1MHz.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1878-1887"},"PeriodicalIF":5.2,"publicationDate":"2024-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

In-Memory Implementation of an Approximate Adder With Reduced Latency and Error 减少延迟和错误的近似加法器在内存中的实现

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-18 DOI: 10.1109/TCSI.2024.3511955

Vijaya Lakshmi;Vikramkumar Pudi;John Reuben

{"title":"In-Memory Implementation of an Approximate Adder With Reduced Latency and Error","authors":"Vijaya Lakshmi;Vikramkumar Pudi;John Reuben","doi":"10.1109/TCSI.2024.3511955","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3511955","url":null,"abstract":"In-memory computing has been a prominent solution to Von Neumann bottleneck that degrades the performance of a computing system. Approximate computing is widely used to improve the performance of multimedia and other applications that are error-tolerant. Approximate adders being the basic units used to design other complex units, get benefited when implemented in-memory by taking the advantages of both in-memory computing and approximate computing. In this work, we have improved the speculative carry select adder to minimize error and critical path delay by eliminating multiplexers. The proposed adder achieves less critical path, area, improved error characteristics such as error rate, normalized mean error distance and mean relative error distance when compared to the state-of-the-art approximate adders. Error rate of the proposed adder is 34.48% less than the best reported 32-bit adder with sub-adder size of 8-bit. When the proposed approximate adders are implemented in-memory using majority logic, they achieve better performance compared to the existing in-memory approximate adders. Latency of the proposed adders is observed to be a constant irrespective of adder size for a fixed sub-adder size.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2128-2138"},"PeriodicalIF":5.2,"publicationDate":"2024-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0