IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

{"title":"A High-Efficiency RFEH System With Feedback-Free Fast (F3) MPPT Over a Wide Input Range","authors":"Xufeng Liao;Yuxiang Zhang;Yukai Zhang;Shaohua Zhang;Zhangming Zhu;Lianxi Liu","doi":"10.1109/TCSI.2025.3542823","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3542823","url":null,"abstract":"This paper presents a high-efficiency, wide-input power range ambient Radio Frequency Energy Harvester (RFEH) system, which comprises an adaptive 4-mode impedance matching network (IMN), a single-stage cross-coupled differential-drive (CCDD) rectifier, a maximum power point tracking (MPPT) circuit, and a power manager unit (PMU). To adaptively configure the impedance matching network and modulate the T_ON of the buck-boost converter, a feedback-free fast (F³) MPPT technique based on the input power detection and parameters direct adjustment is proposed. It can effectively address the trade-off between the speed and accuracy in the impedance matching as well as in the maximum power transmission. Therefore, the power conversion efficiency (PCE) of the proposed RFEH system has been greatly improved. The power manager unit (PMU) is composed of a buck-boost converter, a self-supply unit, and a load regulator, which is employed to implement the F³ MPPT, startup, and self-powered of the RFEH system. The proposed design is fabricated in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS technology, and the chip area is about <inline-formula> <tex-math>$1.52times 0.78$ </tex-math></inline-formula> mm². The measurement results demonstrate that the proposed RFEH system can operate in a wide P_IN range of −23 to 1 dBm with over 96% MPPT accuracy. It achieves PCE >20% in the P_IN range of −17 dBm to 1 dBm, with a peak PCE of 49.4% at P<inline-formula> <tex-math>$_{mathrm {IN}}= -5$ </tex-math></inline-formula> dBm.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2592-2602"},"PeriodicalIF":5.2,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stabilization of Markov Jump Systems With Delay by Discrete-Time Aperiodically Intermittent Stochastic Control Based on Lévy Noise","authors":"Xin Liu;Pei Cheng;Feiqi Deng;Ting Cai","doi":"10.1109/TCSI.2025.3541034","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3541034","url":null,"abstract":"This paper investigates how to stabilize unstable Markov jump systems with delay (MJSs-D) using non-Gaussian white noise based on sampled observations. First, the study addresses the noise stabilization problem of the corresponding delay-free Markov jump systems (MJSs). Using the Lyapunov function method and the stationary distribution of Markov chains, an aperiodic intermittent stochastic control based on Lévy noise (AISC-LN) is developed. The analysis of the low-order moment exponential stability of stochastic controlled systems is comprehensively based on the ergodicity of the Markov chain, making the derived criterion less restrictive than the traditional one under <italic>M</i>-matrix-based conditions. Subsequently, leveraging the auxiliary system method and comparison principle, the AISC-LN based on discrete-time state and mode observations is proposed for MJSs-D. This strategy encompasses specific cases such as discrete-time feedback control and periodic intermittent control based on Brownian motion, furthermore highlights the stabilizing effects of Markov chains and Poisson white noise, thereby providing a definitive answer to the proposed problem. The new control scheme applies to MJSs-D with various types of relatively small delays. Finally, the feasibility and accuracy of the conclusions are validated through an example of a DC-DC buck converter circuit.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2878-2889"},"PeriodicalIF":5.2,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Distributed Composite Learning Dynamic Event-Triggered Control for Nonlinear Multi-Agent Power Systems","authors":"Tongxin Shi;Longsheng Chen;Guoyi He;Wei Song","doi":"10.1109/TCSI.2025.3539299","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3539299","url":null,"abstract":"In this paper, a distributed composite learning dynamic event-triggered (ET) control protocol is presented for nonlinear multi-agent power systems (NMAPSs) in the presence of switching topologies, uncertain nonlinearities, external disturbances and limited network resources. A predictor-based continuous emotional self-structuring neural network (NN) is proposed to approximate unknown nonlinearities of NMAPSs. Flexible structure and emotion-based approaches not only can balance the contradiction between computational burden and control performance but also keep a fast response property of NN approximate. The predictor can improve the approximation accuracy and interpretability of NN approximate by introducing a prediction error to update NN’s weights. Next, a dynamic ET mechanism is presented, which introduces a dynamic self-regulation variable to prolong the ET interval. On this basis, the designed control protocol is sent to actuator only at the ET instant to further reduce the network burden. Then, a distributed composite learning control protocol is developed for NMAPSs by utilizing the Lyapunov stability theorem. It can guarantee that all signals in the closed-loop system are bounded under a class of switching topologies with the average dwell time, and the Zeno phenomenon is avoided ultimately. Finally, simulation results are provided to demonstrate the effectiveness of the proposed protocol.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2274-2287"},"PeriodicalIF":5.2,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Power Quality in Class-D High-Frequency Power Inverter: Input and Resonant Tank Distortion Power, Total Harmonic Distortion, and Power Factor","authors":"Marian K. Kazimierczuk;Fabio Corti;Gabriele Maria Lozito;Alberto Reatti","doi":"10.1109/TCSI.2025.3538106","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3538106","url":null,"abstract":"This paper presents a power quality evaluation of the Class-D high-frequency power amplifier/inverter. The real, reactive, complex, apparent, distortion, and non-active powers at the input of the resonant circuit are derived and illustrated as functions of frequency. Also, the total harmonic distortion and power factor are determined. Similar analysis of the power quality at the dc input of the amplifier is given. Experimental results are given to verify the theory. It is shown that the input current of the Class-D inverter contains a significant ac component that does not contribute to the real dc input power, resulting in high distortion power, high total harmonic distortion, and poor power factor. The Class-D inverter was designed, built and tested to verify the theory.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2419-2431"},"PeriodicalIF":5.2,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Investigation on the Three-Dimensional Memristive Morris–Lecar Model With Magnetic Induction Effects: Simulation of Biological Behaviors and Cost-Effective Digital Circuit Implementation","authors":"Jun Sun;Huan Chen;Xiaojun Ji;Guodao Zhang;Chaochao Wang;Xinjun Miao","doi":"10.1109/TCSI.2025.3534329","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3534329","url":null,"abstract":"The use of FPGA technology is becoming more popular for integrating neuromorphic computing systems because of the parallel processing capabilities and flexibility it offers. This study investigates the implementation of the 3D-Morris Lecar neuronal system, known as Digital Optimized Morris Lecar (DOML), in circuits to characterize the magnetic induction flow induced by neuron membrane potential. By employing a combination of trigonometric functions, hyperbolic functions, power-2 based terms, and LUT-based modules, a high-performance circuit is achieved through the best approximation methods. The model’s effectiveness is verified through validation techniques and error analysis, demonstrating a low-error mechanism due to the approximation of nonlinear functions and the avoidance of multipliers, dividers, and high-cost terms. By utilizing the proposed DOML method in digital synthesized circuits, a potential reduction of up to 37% in FPGA hardware resource cost and a potential speed increase of up to 5 times are achievable. The models were digitally synthesized using the Xilinx FPGA Virtex-4 board for cost-frequency validation, showing that the proposed model outperforms the original ML3D model while preserving its essential characteristics. The novelty of this approach lies in applying the combined approximation methods to create a cost-effective circuit suitable for biological systems, offering high speed and low cost attributes. Then, this basic circuit is applied in a sample Network of DOMLs (as a case study) to simulate and realize the population approach in simple form. This research’s findings can have practical implications for the development of neuromorphic hardware in medical devices, particularly in brain-computer interfaces and neuroprosthetics, where high-performance, low-cost hardware is crucial. In large-scale networks, our proposed modeling can be applied which is investigated in case of DOML connections.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2690-2700"},"PeriodicalIF":5.2,"publicationDate":"2025-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ferroelectric FET-Based Bayesian Inference Engine for Disease Diagnosis","authors":"Arka Chakraborty;Musaib Rafiq;Yawar Hayat Zarkob;Yogesh Singh Chauhan;Shubham Sahay","doi":"10.1109/TCSI.2025.3533044","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3533044","url":null,"abstract":"Probabilistic/stochastic computations form the backbone of autonomous systems and classifiers. Recently, biomedical applications of probabilistic computing such as Bayesian networks for disease diagnosis, DNA sequencing, etc. have attracted significant attention owing to their high energy-efficiency. Bayesian inference is widely used for decision making based on independent (often conflicting) sources of information/evidence. A cascaded chain or tree structure of asynchronous circuit elements known as Muller C-elements can effectively implement Bayesian inference. Such circuits utilize stochastic bit streams to encode input probabilities which enhances their robustness and fault-tolerance. However, the CMOS implementations of Muller C-element are bulky and energy hungry which restricts their widespread application in resource constrained IoT and mobile devices such as UAVs, robots, space rovers, etc. In this work, for the first time, we propose a compact and energy-efficient implementation of Muller C-element utilizing a single Ferroelectric FET and use it for cancer diagnosis task by performing Bayesian inference with high accuracy on Wisconsin data set. The proposed implementation exploits the unique drain-erase, program inhibit and drain-erase inhibit characteristics of FeFETs to yield the output as the polarization-state of the ferroelectric layer. Our extensive investigation utilizing an in-house developed experimentally calibrated compact model of FeFET reveals that the proposed C-element consumes (worst-case) energy of 4.1 fJ and an area <inline-formula> <tex-math>$0.07~mu m^{2}$ </tex-math></inline-formula> and outperforms the prior implementations in terms of energy-efficiency and footprint while exhibiting a comparable delay. We also propose a novel read circuitry for realising a Bayesian inference engine by cascading a network of proposed FeFET-based C-elements for practical applications. Furthermore, for the first time, we analyze the impact of cross-correlation between the stochastic input bit streams on the accuracy of the C-element based Bayesian inference implementation.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1547-1559"},"PeriodicalIF":5.2,"publicationDate":"2025-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Adaptive Switching Control for Nonlinear Uncertain Systems With Sensor Faults and Quantization","authors":"Xianglei Jia;Shengyuan Xu;Guozeng Cui","doi":"10.1109/TCSI.2025.3537719","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3537719","url":null,"abstract":"In this article, global adaptive quantized control problem of a class of nonlinear uncertain systems with sensor faults is addressed, and a novel non-identification adaptive control method is proposed based on a switching mechanism. One advantage of the proposed method is that continuous multiplicative sensor faults are tolerated and handled in a generalized Lyapunov matrix inequality; another is its lower computational complexity compared to the traditional adaptive backstepping method (avoiding the ‘differential explosion’ problem). In addition, a new hysteresis logarithmic-type quantizer is developed to prevent chattering. The quantization error is dealt with by using sector bounded property, where the compensation of multiplicative deviation in quantization is similar to that of multiplicative sensor faults, while additive bias is treated as a disturbance (quantization dead-zone size determines the magnitude of the disturbance). Especially, the relationship between quantization dead-zone and control accuracy is clearly characterized. Also, it is shown that the proposed control method is robust to mismatched disturbances, and the solutions of the closed-loop system can be guaranteed to converge to the arbitrarily small neighborhood of the origin as long as the dead-zone of quantizer and mismatched disturbances are sufficiently small.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2832-2841"},"PeriodicalIF":5.2,"publicationDate":"2025-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 0.07 pJ/b/dB 36-Gb/s PAM-3 Receiver Using Inductor-Reused CTLE and One-Tap Loop-Unrolled DFE in 22-nm CMOS","authors":"Pin-Yuan Chiu;Shen-Iuan Liu","doi":"10.1109/TCSI.2025.3536091","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3536091","url":null,"abstract":"This paper presents a 36 Gb/s (23.04 GBaud) 3-level pulse amplitude modulation (PAM-3) receiver (RX). The proposed inductor-reused continuous-time linear equalizer (CTLE) uses feedforward and inductive peaking techniques. Additionally, the number of the data slicers is reduced in the PAM-3 receiver with a loop-unrolled decision feedback equalizer (DFE). Furthermore, a baud-rate phase detector (BRPD) is presented. Fabricated in 22-nm CMOS technology, this receiver compensates for a channel loss of 20.5 dB at 11.52 GHz, achieving a bit error rate (BER) of less than <inline-formula> <tex-math>$10^{-12} $ </tex-math></inline-formula> with a pseudo-random ternary sequence (PRTS) of <inline-formula> <tex-math>$3^{7}mathbf {-}1$ </tex-math></inline-formula>. The measured clock integrated jitter is 267 fsrms at 720 MHz, and the retimed data exhibits 10.98 pspp jitter. The overall receiver consumes 51.7 mW, with a calculated energy efficiency of 1.44 pJ/b and a figure of merit (FoM) of 0.07 pJ/b/dB.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1522-1532"},"PeriodicalIF":5.2,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Single-Input Multi-Output Resonant Regulating Rectifier Generating Three Outputs in a Half Cycle for Wirelessly Powered Biomedical Devices","authors":"Hyun-Su Lee;Kyeongho Eom;Hyung-Min Lee","doi":"10.1109/TCSI.2025.3531211","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3531211","url":null,"abstract":"This paper introduces single-input multi-output (SIMO) resonant regulating rectifier (R<italic>³</i>) designed to produce three regulated outputs in a half cycle without low drop-out (LDO) regulators. Utilizing distributed multi-phase control allows for the regulation of three outputs in a half cycle, leading to increased power delivered to the load (PDL), reduced output ripple, and a higher number of outputs. Additionally, the adoption of negative threshold gate driver (NTGD) and a hybrid high/low comparator (HCMP) enhances the output voltage regulation range and power conversion efficiency (PCE). To ensure the safe control of three distinct outputs in a half cycle, all three outputs are equipped with end protection techniques. Moreover, for a secure start-up of the secondary outputs, the proposed pre-biasing technique in the pulse width modulation (PWM) controller is implemented. The 1.54-mm<inline-formula> <tex-math>$^{2}~0.25$ </tex-math></inline-formula>-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS SIMO R³ demonstrates the capability to generate three regulated outputs, with a maximum primary voltage and minimum secondary voltage difference of up to 3.5 V. Furthermore, a PCE of 90.82% is achieved with a total load power of 84.6 mW. These advancements position the SIMO R³, especially with dynamic voltage scaling (DVS) stimulation, as a promising solution for efficient use in retinal prostheses.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2956-2969"},"PeriodicalIF":5.2,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Polynomial Formal Verification of Multi-Valued Approximate Circuits Within Constant Cutwidth","authors":"Mohamed Nadeem;Chandan Kumar Jha;Rolf Drechsler","doi":"10.1109/TCSI.2025.3531008","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3531008","url":null,"abstract":"Ensuring functional correctness is achieved through formal verification. As circuit complexity increases, limiting the upper bounds for time and space required for verification becomes crucial. Polynomial Formal Verification (PFV) has been introduced to tackle this problem. In modern digital system designs, approximate circuits are widely employed in error resilient applications. Therefore, ensuring the functional correctness of these circuits becomes essential. In prior works, it has been proven that approximate circuits with constant cutwidth can be verified in linear time. However, extending binary logic verification to Multi-Valued Logic (MVL) introduces challenges, particularly regarding the encoding of MVL operators. It has been shown that MVL circuits with constant cutwidth can be verified in linear time using Answer Set Programming (ASP), due to the ASP encoding capabilities of MVL operators. In this paper, we present a PFV approach of MVL approximate circuits with constant cutwidth using ASP. We then demonstrate that the verification of MVL approximate circuits with constant cutwidth can be achieved in linear time. Finally, we evaluate various MVL approximate circuits with constant cutwidth across different logic levels to show the efficacy of our approach.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1411-1424"},"PeriodicalIF":5.2,"publicationDate":"2025-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}