MINA:用于可穿戴设备心电分类的硬件高效和灵活的Mini-InceptionNet加速器

IF 5.2 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC
Hoai Luan Pham;Thi Diem Tran;Vu Trung Duong Le;Yasuhiko Nakashima
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引用次数: 0

摘要

分类是心血管相关挑战的一个关键方面,需要深入研究和优化,为患者和医生制定有效的解决方案。近年来,人工智能,特别是卷积神经网络(cnn)的快速发展,引入了许多有效的方法,显著改善了心电图(ECG)分析中的疾病分类。然而,现有的基于CNN的加速器经常遇到诸如参数数量高、处理各种CNN配置的灵活性有限以及硬件利用率低等挑战。为了解决这些问题,本文提出了Mini InceptionNet加速器(MINA),这是一种硬件高效且灵活的加速器,专为一维(1-D) cnn心电分类而设计。首先,与现有最小的1-D CNN相比,一种新的1-D CNN模型Mini InceptionNet减少了41.6%的参数计数,在保持高分类精度的同时最大限度地减少了内存需求。其次,设计了一个灵活的处理单元阵列(PEA)和共享缓冲区分配器(SBA),以支持跨各种网络拓扑参数的动态数据协调。第三,每个处理单元(PE)配备四个本地数据存储器(ldm)和一个ALU,为现代CNN模型提供高效的中间数据存储和通用操作。为了证明其有效性,MINA已在ZCU102 FPGA上成功实现并在片上系统级进行了验证。FPGA评估表明,MINA的能效(GOP/s/MeLUT)比最先进的2d CNN加速器高1.3 - 2.9倍。与现有的1-D CNN加速器相比,MINA在面积延迟积(ADP)方面实现了至少1.53倍的改进。此外,权重修剪作为一种支持策略进行了讨论,在70%稀疏度下实现了高达3倍的推理时间和2.13倍的ADP改进。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
MINA: A Hardware-Efficient and Flexible Mini-InceptionNet Accelerator for ECG Classification in Wearable Devices
Classification is a crucial aspect of cardiovascular-related challenges, requiring thorough research and optimization to develop effective solutions for both patients and doctors. Recently, rapid advancements in artificial intelligence, particularly Convolutional Neural Networks (CNNs), have introduced numerous effective methods, significantly improving disease classification in Electrocardiogram (ECG) analysis. However, existing CNN-based accelerators often encounter challenges such as high parameter counts, limited flexibility in handling diverse CNN configurations, and inefficient hardware utilization. To address these issues, this paper proposes the Mini InceptionNet Accelerator (MINA), a hardware-efficient and flexible accelerator designed specifically for one-dimensional (1-D) CNN-based ECG classification. First, a novel 1-D CNN model, Mini InceptionNet, reduces the parameter count by 41.6% compared to the smallest existing 1-D CNN, minimizing memory requirements while maintaining high classification accuracy. Second, a flexible Processing Element Array (PEA) is designed with a Sharing Buffer Allocator (SBA) to support dynamic data coordination across various network topology parameters. Third, each Processing Element (PE) is equipped with four Local Data Memories (LDMs) and an ALU, enabling efficient intermediate data storage and versatile operations for modern CNN models. To demonstrate its effectiveness, MINA has been successfully implemented and verified on the ZCU102 FPGA at the system-on-chip level. FPGA evaluations show that MINA achieves $1.3\times - 2.9\times $ higher energy efficiency (GOP/s/MeLUT) than state-of-the-art 2-D CNN accelerators. Compared to existing 1-D CNN accelerators, MINA achieves at least $1.53\times $ improvement in the area-delay product (ADP). Additionally, weight pruning is discussed as a supporting strategy, achieving up to $3\times $ faster inference time and a $2.13\times $ improvement in ADP at 70% sparsity.
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来源期刊
IEEE Transactions on Circuits and Systems I: Regular Papers
IEEE Transactions on Circuits and Systems I: Regular Papers 工程技术-工程:电子与电气
CiteScore
9.80
自引率
11.80%
发文量
441
审稿时长
2 months
期刊介绍: TCAS I publishes regular papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: - Circuits: Analog, Digital and Mixed Signal Circuits and Systems - Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic - Circuits and Systems, Power Electronics and Systems - Software for Analog-and-Logic Circuits and Systems - Control aspects of Circuits and Systems.
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