A Neuromorphic Transformer Architecture Enabling Hardware-Friendly Edge Computing

IF 5.2 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC
P. J. Zhou;R. C. Ma;Y. C. Chen;Z. T. Liu;C. Y. Liu;L. W. Meng;G. C. Qiao;Y. Liu;Q. Yu;S. G. Hu
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引用次数: 0

Abstract

The transformer model has demonstrated significant capabilities in various intelligent tasks, attracting widespread attention in recent years. However, it involves numerous complex operations, including large-bit-width multiplication, division, matrix transposition, and exponentiation. These require substantial storage and computational resources, making it challenging to deploy on edge devices. This work introduces a neuromorphic transformer architecture with low hardware cost for AI edge computing (AI-EC). At the structural level, it absorbs scaling factors within the self-attention mechanism into weight matrixes, thereby eliminating the division caused by the scaling operation. Additionally, a transposition calculation method is proposed to perform matrix transposition using dedicated memory access strategies and optimized data flow designs, which reduces logic resource overhead and avoids memory access discontinuities. At the computing paradigm level, the architecture employs spike-driven computing, substituting multi-bit multipliers with AND logic for synaptic operations. The paradigm introduces high sparsity to computational data, which is effectively exploited to reduce the computational workload of the architecture. The results indicate that the architecture successfully eliminates high-cost operators and significantly reduces computational expenses. Eventually, this architecture is verified as a prototype using a 28 nm CMOS process library, demonstrating a compact logic area of sub-0.2 mm2 and a high energy efficiency of 0.34 pJ/SOP @ 50MHz. This work is expected to promote the application of transformers in edge computing and the development of intelligent edge applications.
一种支持硬件友好边缘计算的神经形态转换器架构
变压器模型在各种智能任务中显示出显著的能力,近年来引起了广泛的关注。然而,它涉及许多复杂的操作,包括大比特宽的乘法、除法、矩阵转置和求幂。这些都需要大量的存储和计算资源,这使得在边缘设备上部署具有挑战性。本文介绍了一种低硬件成本的神经形态转换器架构,用于人工智能边缘计算(AI- ec)。在结构层面,它将自注意机制内的标度因子吸收到权重矩阵中,从而消除了标度操作造成的分割。此外,提出了一种利用专用内存访问策略和优化数据流设计进行矩阵转置的转置计算方法,减少了逻辑资源开销,避免了内存访问不连续。在计算范式层面,该架构采用峰值驱动计算,用与逻辑代替多比特乘法器进行突触操作。该范式为计算数据引入了高稀疏性,有效地利用了这一点来减少体系结构的计算工作量。结果表明,该体系结构成功地消除了高成本运算符,显著降低了计算费用。最终,该架构使用28纳米CMOS工艺库作为原型进行验证,展示了低于0.2 mm2的紧凑逻辑面积和0.34 pJ/SOP @ 50MHz的高能效。这项工作有望推动变压器在边缘计算中的应用和智能边缘应用的发展。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Transactions on Circuits and Systems I: Regular Papers
IEEE Transactions on Circuits and Systems I: Regular Papers 工程技术-工程:电子与电气
CiteScore
9.80
自引率
11.80%
发文量
441
审稿时长
2 months
期刊介绍: TCAS I publishes regular papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: - Circuits: Analog, Digital and Mixed Signal Circuits and Systems - Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic - Circuits and Systems, Power Electronics and Systems - Software for Analog-and-Logic Circuits and Systems - Control aspects of Circuits and Systems.
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