基于电感gnn的综合ASIC设计平均功率准确快速估算方法

IF 5.2 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC
M. B. Rakesh;Pabitra Das;K. R. Sai Pranav;Amit Acharyya
{"title":"基于电感gnn的综合ASIC设计平均功率准确快速估算方法","authors":"M. B. Rakesh;Pabitra Das;K. R. Sai Pranav;Amit Acharyya","doi":"10.1109/TCSI.2025.3555891","DOIUrl":null,"url":null,"abstract":"This paper proposes an inductive Graph Neural Network (GNN) based methodology for accurate and fast average power estimation of logic-synthesized and RTL-simulated ASIC Design, eliminating gate-level simulation. With the novel variation of inductive GNN architecture, the proposed model propagates the input wires’ toggle rates acquired from RTL simulation through the synthesized design. We only train the proposed model on circuits synthesized from TSMC 65nm technology node but test on the circuits synthesized across TSMC 65nm, 40nm, 90nm, 130nm and GF 40nm technology nodes. We test the inductivity of the proposed model to predict the output wires’ toggle rates of unseen and untrained logic cells of the designs. We compute the proposed methodology’s average power inference throughput (number of cycles inferred per second) for speed comparison. The proposed model does better than state-of-the-art architecture GRANNITE to predict the unseen and untrained logic cell’s toggle rates of the designs across TSMC 65nm, 40nm, 90nm, 130nm, and GF 40nm technology nodes, showing an average improvement of 6.67%, 8.49%, 9.26%, 7.47% and 6.36%, respectively. The proposed methodology is more accurate than the commercial RTL average power estimation tool and GRANNITE in estimating the average power of circuits across TSMC 65nm, 40nm, 90nm, 130nm, and GF 40nm technology nodes by achieving a mean improvement of 24.94%, 16.77%, 17.65%, 29.72%, and 32.84%; 2.75%, 1.1%, 1.81%, 2.59% and 4.49%; respectively. The proposed methodology is 11.07X faster, with an average inference throughput of 1.218kHz, than the commercial gate-level average power estimation tool.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2818-2831"},"PeriodicalIF":5.2000,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Inductive GNN-Based Methodology for Accurate and Fast Average Power Estimation of Synthesized ASIC Designs From RTL Simulation Bypassing Gate-Level Simulation\",\"authors\":\"M. B. Rakesh;Pabitra Das;K. R. Sai Pranav;Amit Acharyya\",\"doi\":\"10.1109/TCSI.2025.3555891\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes an inductive Graph Neural Network (GNN) based methodology for accurate and fast average power estimation of logic-synthesized and RTL-simulated ASIC Design, eliminating gate-level simulation. With the novel variation of inductive GNN architecture, the proposed model propagates the input wires’ toggle rates acquired from RTL simulation through the synthesized design. We only train the proposed model on circuits synthesized from TSMC 65nm technology node but test on the circuits synthesized across TSMC 65nm, 40nm, 90nm, 130nm and GF 40nm technology nodes. We test the inductivity of the proposed model to predict the output wires’ toggle rates of unseen and untrained logic cells of the designs. We compute the proposed methodology’s average power inference throughput (number of cycles inferred per second) for speed comparison. The proposed model does better than state-of-the-art architecture GRANNITE to predict the unseen and untrained logic cell’s toggle rates of the designs across TSMC 65nm, 40nm, 90nm, 130nm, and GF 40nm technology nodes, showing an average improvement of 6.67%, 8.49%, 9.26%, 7.47% and 6.36%, respectively. The proposed methodology is more accurate than the commercial RTL average power estimation tool and GRANNITE in estimating the average power of circuits across TSMC 65nm, 40nm, 90nm, 130nm, and GF 40nm technology nodes by achieving a mean improvement of 24.94%, 16.77%, 17.65%, 29.72%, and 32.84%; 2.75%, 1.1%, 1.81%, 2.59% and 4.49%; respectively. The proposed methodology is 11.07X faster, with an average inference throughput of 1.218kHz, than the commercial gate-level average power estimation tool.\",\"PeriodicalId\":13039,\"journal\":{\"name\":\"IEEE Transactions on Circuits and Systems I: Regular Papers\",\"volume\":\"72 6\",\"pages\":\"2818-2831\"},\"PeriodicalIF\":5.2000,\"publicationDate\":\"2025-04-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Circuits and Systems I: Regular Papers\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10964401/\",\"RegionNum\":1,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems I: Regular Papers","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10964401/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

摘要

本文提出了一种基于归纳图神经网络(GNN)的方法,用于快速准确地估计逻辑合成和rtl仿真ASIC设计的平均功率,消除了门级仿真。该模型利用感应式GNN结构的新变化,通过综合设计传播从RTL仿真中获得的输入线的切换率。我们只在台积电65nm技术节点合成的电路上训练所提出的模型,但在台积电65nm、40nm、90nm、130nm和GF 40nm技术节点合成的电路上进行了测试。我们测试了所提出模型的电感率,以预测设计中未见和未训练的逻辑单元的输出线切换率。我们计算了所提出方法的平均功率推断吞吐量(每秒推断的周期数)以进行速度比较。该模型在预测TSMC 65nm、40nm、90nm、130nm和GF 40nm技术节点上未见和未训练逻辑单元的切换率方面优于GRANNITE,平均分别提高了6.67%、8.49%、9.26%、7.47%和6.36%。该方法在TSMC 65nm、40nm、90nm、130nm和GF 40nm技术节点上的电路平均功率估计比商用RTL平均功率估计工具和GRANNITE更准确,平均提高24.94%、16.77%、17.65%、29.72%和32.84%;2.75%、1.1%、1.81%、2.59%、4.49%;分别。所提出的方法比商用门级平均功率估计工具快11.07倍,平均推断吞吐量为1.218kHz。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Inductive GNN-Based Methodology for Accurate and Fast Average Power Estimation of Synthesized ASIC Designs From RTL Simulation Bypassing Gate-Level Simulation
This paper proposes an inductive Graph Neural Network (GNN) based methodology for accurate and fast average power estimation of logic-synthesized and RTL-simulated ASIC Design, eliminating gate-level simulation. With the novel variation of inductive GNN architecture, the proposed model propagates the input wires’ toggle rates acquired from RTL simulation through the synthesized design. We only train the proposed model on circuits synthesized from TSMC 65nm technology node but test on the circuits synthesized across TSMC 65nm, 40nm, 90nm, 130nm and GF 40nm technology nodes. We test the inductivity of the proposed model to predict the output wires’ toggle rates of unseen and untrained logic cells of the designs. We compute the proposed methodology’s average power inference throughput (number of cycles inferred per second) for speed comparison. The proposed model does better than state-of-the-art architecture GRANNITE to predict the unseen and untrained logic cell’s toggle rates of the designs across TSMC 65nm, 40nm, 90nm, 130nm, and GF 40nm technology nodes, showing an average improvement of 6.67%, 8.49%, 9.26%, 7.47% and 6.36%, respectively. The proposed methodology is more accurate than the commercial RTL average power estimation tool and GRANNITE in estimating the average power of circuits across TSMC 65nm, 40nm, 90nm, 130nm, and GF 40nm technology nodes by achieving a mean improvement of 24.94%, 16.77%, 17.65%, 29.72%, and 32.84%; 2.75%, 1.1%, 1.81%, 2.59% and 4.49%; respectively. The proposed methodology is 11.07X faster, with an average inference throughput of 1.218kHz, than the commercial gate-level average power estimation tool.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
IEEE Transactions on Circuits and Systems I: Regular Papers
IEEE Transactions on Circuits and Systems I: Regular Papers 工程技术-工程:电子与电气
CiteScore
9.80
自引率
11.80%
发文量
441
审稿时长
2 months
期刊介绍: TCAS I publishes regular papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: - Circuits: Analog, Digital and Mixed Signal Circuits and Systems - Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic - Circuits and Systems, Power Electronics and Systems - Software for Analog-and-Logic Circuits and Systems - Control aspects of Circuits and Systems.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信