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1992 Proceedings 42nd Electronic Components & Technology Conference最新文献

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The 3D stack in short form (memory chip packaging) 简写的3D堆栈(存储芯片封装)
1992 Proceedings 42nd Electronic Components & Technology Conference Pub Date : 1992-05-18 DOI: 10.1109/ECTC.1992.204230
J. Minahan, A. Pepe, R. Some, M. Suer
{"title":"The 3D stack in short form (memory chip packaging)","authors":"J. Minahan, A. Pepe, R. Some, M. Suer","doi":"10.1109/ECTC.1992.204230","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204230","url":null,"abstract":"A novel form of 3D high-density stack, called a short stack, has been built and tested. One version of the short stack allowed accurate measurement of the T-connect resistance, approximately=0.025 ohms, while a second version was designed to provide four memory chips stacked for use in a low headroom application that incorporated the 3D technology with the high-density interconnect multichip approach.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134536617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Integral heatsink polysilicon semiconductor packaging 集成散热器多晶硅半导体封装
1992 Proceedings 42nd Electronic Components & Technology Conference Pub Date : 1992-05-18 DOI: 10.1109/ECTC.1992.204299
M. McGeary
{"title":"Integral heatsink polysilicon semiconductor packaging","authors":"M. McGeary","doi":"10.1109/ECTC.1992.204299","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204299","url":null,"abstract":"To evaluate some of the claims made in patent applications, UK 90 14491.6 and US 07/722,741 single-chip and multichip packages were fabricated from polycrystalline silicon (p:Si) with integral, p:Si, cooling fins. By using die-sized pieces of ceramic patterned with a platinum heater (of known temperature coefficient of resistance) data were recorded of heater temperature for a range of input wattages and different cooling conditions. The data are presented as heater temperature (corresponding to device junction temperature) above ambient, against a range of electrical input wattages for seven different package configurations cooled by convection and by forced air. Experimental results indicate that integral heatsink polycrystalline silicon packages for silicon semiconductor devices provide better thermal characteristics than existing ceramic packages.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115538684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A thick film package for microwave ICs 微波集成电路的厚膜封装
1992 Proceedings 42nd Electronic Components & Technology Conference Pub Date : 1992-05-18 DOI: 10.1109/ECTC.1992.204199
R. Gutiérrez, H. M. Olson, D. R. Decker
{"title":"A thick film package for microwave ICs","authors":"R. Gutiérrez, H. M. Olson, D. R. Decker","doi":"10.1109/ECTC.1992.204199","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204199","url":null,"abstract":"A rugged, inexpensive two-port package for mounting a cascade of monolithic microwave ICs was developed. The package consists of two layers of alumina on which silk-screened metal pastes are deposited to form the metal patterns. The RF design of the conductors is described, and the measured transmission properties of the package are given. The key to achieving low insertion loss at microwave frequencies is to use a process that keeps the conductor resistivity as low as possible. It is also important to avoid reflections at discontinuities. It was possible to achieve reasonably smooth insertion loss characteristics and low return loss up to 6 GHz. This required the suppression of parallel-plate waveguide modes and the careful design of the transmission lines for correct characteristic impedance. The suppression of parallel-plate waveguide resonances is achieved by the introduction of via walls along the transmission lines.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115903020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Relative figures of merit for potential chip-to-MCM substrate interconnection methods for CMOS and ECL multichip packaging CMOS和ECL多芯片封装中潜在的芯片- mcm衬底互连方法的相对优点图
1992 Proceedings 42nd Electronic Components & Technology Conference Pub Date : 1992-05-18 DOI: 10.1109/ECTC.1992.204281
U. Shrivastava, W. Valentine, M. Mahalingam
{"title":"Relative figures of merit for potential chip-to-MCM substrate interconnection methods for CMOS and ECL multichip packaging","authors":"U. Shrivastava, W. Valentine, M. Mahalingam","doi":"10.1109/ECTC.1992.204281","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204281","url":null,"abstract":"Results of a comparative study of the performance of 45 simultaneously switching 8-mA CMOS off chip drivers per chip and of 140 emitter follower drivers per ECL (emitter coupled logic) chip in various multichip module (MCM) scenarios are reported. The analysis was made for multichip systems using 12.7-mm*12.7-mm ICs. High-density substrate technology is essential for realizing the performance levels reported. Up to twelvefold (sevenfold for ECL) improvement in performance over TAB (tape automated bonding) is possible with the flip chip technology in CMOS (ECL) systems. When the propagation delay in the critical path in the multichip system is dominated by the internal gates, the speed figure of merit approaches unity. Electrical parasitics of the chip to substrate interconnections induce undershoot in the switching signal, which reduces the noise margin. Interconnection length is a major factor in determining the performance and noise for multichip packaging. This analysis shows that the flip chip technology provides the highest multichip system.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116260358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Equivalent circuit modeling of interconnects from time domain measurements 基于时域测量的互连等效电路建模
1992 Proceedings 42nd Electronic Components & Technology Conference Pub Date : 1992-05-18 DOI: 10.1109/ECTC.1992.204285
J. Jong, V. Tripathi, B. Janko
{"title":"Equivalent circuit modeling of interconnects from time domain measurements","authors":"J. Jong, V. Tripathi, B. Janko","doi":"10.1109/ECTC.1992.204285","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204285","url":null,"abstract":"A technique for the equivalent circuit modeling of interconnects having discontinuities such as bends, steps, and junctions in high-speed circuits and packages is developed. The circuit models are extracted from time domain reflection (TDR) measurements. The simulated results for the circuit models are compared with the measured data to validate the accuracy of the circuit model. The proposed method can be used to help validate circuit models based on field-theoretic techniques as well as used as an independent tool to synthesize circuit models for general nonuniform or interacting two- and three-dimensional interconnects.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115140817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 74
Prediction and measurement of thermal conductivity of diamond filled adhesives 金刚石填充胶粘剂导热系数的预测与测量
1992 Proceedings 42nd Electronic Components & Technology Conference Pub Date : 1992-05-18 DOI: 10.1109/ECTC.1992.204210
J.C. Bolger
{"title":"Prediction and measurement of thermal conductivity of diamond filled adhesives","authors":"J.C. Bolger","doi":"10.1109/ECTC.1992.204210","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204210","url":null,"abstract":"Heat cured epoxy tape adhesives were made with high filler loadings of (a) silver, (b) aluminum, (c) alumina, and (d) diamond powder. For a, b, and c the thermal conductivity agreed with values predicted from the percentage of filler and the k value of the pure filler. For diamond powder, however, the conductivity data extrapolated to a diamond powder k value of only about 300 W/m degrees K. This lower k value is believed to be due to nitrogen impurity atoms in synthetic diamond powder. The k for diamond filled adhesives is therefore higher than for the best previous AlN, BN, Al/sub 2/O/sub 3/, or ZnO filled dielectric adhesives, but is not as high as for previous silver or other metal filled adhesives. For estimation purposes, adhesive conductivity can be predicted from the volume fraction filler and the filler conductivity (using 300 for diamond) via a specified graphical method.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124942468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Partly-additive process for manufacturing high-density printed wiring boards 高密度印刷线路板的部分增材制造工艺
1992 Proceedings 42nd Electronic Components & Technology Conference Pub Date : 1992-05-18 DOI: 10.1109/ECTC.1992.204336
S. Imabayashi, I. Tanaka, H. Kikuchi, M. Watanabe, H. Oka, S. Izumi, Y. Taniguchi, S. Fujita
{"title":"Partly-additive process for manufacturing high-density printed wiring boards","authors":"S. Imabayashi, I. Tanaka, H. Kikuchi, M. Watanabe, H. Oka, S. Izumi, Y. Taniguchi, S. Fujita","doi":"10.1109/ECTC.1992.204336","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204336","url":null,"abstract":"A highly reliable, high-density printed wiring board process called the partly additive process has been developed for manufacturing high-speed digital switching systems. The partly additive process realizes very fine, highly reliable through-holes and circuit patterns at fairly low cost. To realize this process, a specially designed solder-resist that can withstand high temperatures and the high alkalinity of electroless copper plating solution was developed. A new electroless copper plating solution was also developed that can deposit copper having excellent mechanical and electrical properties. The composition of the electroless copper plating solution could be tightly controlled using a newly developed system to automatically monitor and supply solution components accurately.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123543179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The close attached capacitor: a solution to switching noise problems 闭合电容:解决开关噪声问题的一种方法
1992 Proceedings 42nd Electronic Components & Technology Conference Pub Date : 1992-05-18 DOI: 10.1109/ECTC.1992.204261
H. Hashemi, P. Sandborn, D. Disko, R. Evans
{"title":"The close attached capacitor: a solution to switching noise problems","authors":"H. Hashemi, P. Sandborn, D. Disko, R. Evans","doi":"10.1109/ECTC.1992.204261","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204261","url":null,"abstract":"The authors present an analysis of a novel low-cost, post-attach bypassing technique called close attached capacitor (CAC), which offers an attractive alternative to managing switching noise in single or multichip packages. The CAC is a thin flat capacitor, comparable in size to an IC die, that is placed on the active surface of the die and connected to onchip power and ground pads through very short bonds. By locating the CAC on the face of the die, the inductance of chip bonds and associated outer lead bond pads is avoided and less interconnect area is needed. Some environmental testing of the CAC process has been performed, indicating no device parameter degradation when attachment is made to the active surface of a passivated die. CAC design issues are addressed, and the feasibility of manufacturing high-frequency capacitors and their assemblies using conventional reworkable or permanent attach processes is demonstrated. Examples of the integration of CACs in high-performance single chip packages and to chips on multichip modules are shown, and the effectiveness of CACs in the reduction of switching noise is demonstrated.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122162860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Silver-induced volatile species generation from conductive die attach adhesives 银诱导的挥发性物质由导电模附胶产生
1992 Proceedings 42nd Electronic Components & Technology Conference Pub Date : 1992-05-18 DOI: 10.1109/ECTC.1992.204211
T. E. Phillips, N. Dehaas, P.G. Goodwin, R. Benson
{"title":"Silver-induced volatile species generation from conductive die attach adhesives","authors":"T. E. Phillips, N. Dehaas, P.G. Goodwin, R. Benson","doi":"10.1109/ECTC.1992.204211","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204211","url":null,"abstract":"Commercial and model epoxy die-attach adhesives with and without silver filler, were investigated to examine the effect that the silver filler has on the outgassing characteristics of the organic matrix. The materials were subjected to typical temperature processing schedules including cure, preseal bake, and burn-in. The volatile species outgassing during each of the processing periods were analyzed by gas chromatography/mass spectrometry (GC/MS). Thermogravimetric analyses were also performed. It was determined that silver in the adhesive leads to a greater mass loss and a marked change in the outgassing species relative to the same adhesive system without silver. These effects were observed during cure, preseal bake, and burn-in, GC/MS measurements clearly indicated that new chemical species were outgassed when silver was added to the adhesive, suggesting that chemical reactions were occurring at the silver/organic interface.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125590870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Optoelectronic chips and multichip modules 光电芯片和多芯片模块
1992 Proceedings 42nd Electronic Components & Technology Conference Pub Date : 1992-05-18 DOI: 10.1109/ECTC.1992.204298
T. Jannson, R. Chen, F. Lin
{"title":"Optoelectronic chips and multichip modules","authors":"T. Jannson, R. Chen, F. Lin","doi":"10.1109/ECTC.1992.204298","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204298","url":null,"abstract":"A novel concept of optoelectronic chips and multichip modules (MCMs) is presented. This concept is based on direct integration of single-mode optoelectronics with VLSI/ULSI CMOS technology. This concept allows direct communication between silicon chips and modules without implementing GaAs electronics. External electrooptic (EO) modulators and silicon photodetectors are used as transceivers while optical power is provided by continuous wave (CW) laser diodes (LDs). In analogy with multilayer MCM electrical interconnects, multilayer optical interconnects are provided in the form of polymeric light-distributing interconnect-active (LIDIA) substrates. As a result, the integrated waveguide technology is monolithically integrated through LIDIA intrachip, chip-to-chip, and module-to-module substrates with silicon MCM circuitry.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125819636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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