{"title":"Factors governing the loop profile in Au bonding wire","authors":"Y. Ohno, Y. Ohzeki, T. Aso, O. Kitamura","doi":"10.1109/ECTC.1992.204313","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204313","url":null,"abstract":"It is found by studying the factors governing the loop profile in Au bonding wires that the thermal history in forming the ball caused the observed V-shaped hardness distribution in the heat affected zone. It is proved by combining calculation and simulation that the minimum hardness portion is a dominant factor governing the loop height. As recent LSI packaging is becoming thinner and thinner, a low profile wire is required for the bonding wire, which can be developed by utilizing this approach.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115613823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Mita, S. Takagi, T. Kumakura, Yamaguchi, H. Tanaka
{"title":"New design for a leadframe used for high-speed transmission and high-power LSI package","authors":"M. Mita, S. Takagi, T. Kumakura, Yamaguchi, H. Tanaka","doi":"10.1109/ECTC.1992.204246","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204246","url":null,"abstract":"To meet the requirements of high speed driving LSI packages with powerful output, a combination leadframe has been developed which is made up of a two-metal-layer FPC (flexible printed circuit) and an outer leadframe. The use of thin copper foil minimizes the inner-lead pitch to 120 mu m. The combination structure of the FPC and leadframe greatly shortens the surface mounting. The developed method of joining the FPC to the leadframe using Au-Sn eutectic soldering is reliable at high temperatures and temperature cycles. This leadframe has some excellent characteristics. The electrical impedance of the leads can be easily controlled by rearrangement of lead widths, gaps, and dielectric insulation. The heat spreading effect by plain metal, which halved the apparent thermal resistance, is excellent. The adhesiveless copper clad laminate has a positive effect in preventing electromigration.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121338057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. M. D’ambra, M.C.A. Needes, C. Needes, C.B. Wang
{"title":"Via formation in green ceramic dielectrics using a YAG laser","authors":"D. M. D’ambra, M.C.A. Needes, C. Needes, C.B. Wang","doi":"10.1109/ECTC.1992.204339","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204339","url":null,"abstract":"A high-speed laser drilling process has been developed for producing fine-pitch vias of dimensions equivalent to fine-line screen printed conductors. Drilling speeds as high as 150-220 vias per second have been demonstrated on thick film and Green Tape dielectrics using an Nd:YAG laser. Throughputs greater than 300 vias/s could be achieved when multiple layers of Green Tape were drilled at once. There are a number of laser parameters which are critical to achieving high via formation rates while maintaining the accuracy of the via positioning. In addition, the electric composition and its thickness determine the beam power and number of pulses needed to drill each via. The quality of the drilled vias was improved by including a laser absorbing pigment in the dielectric formulation. Overall speed was also dependent upon design parameters such as via pitch, the symmetry of the circuit design, and the drilling sequence.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115954257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A study of failures identified during board level environmental stress testing","authors":"T. Parker, C. W. Webb","doi":"10.1109/ECTC.1992.204204","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204204","url":null,"abstract":"AT&T has investigated and implemented environmental stress testing (EST) in the production of a variety of circuit board designs as a means of reducing the incidence of early life failures. EST techniques include thermal cycling, random vibration, and others. These techniques have proven more effective than traditional burn-in techniques. In addition, studies have revealed that functional monitoring during thermal stressing of circuit cards more than doubles the effectiveness of EST. Outgoing quality audits and customer first month failure rates have improved by factors of two to four since the implementation of EST.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"1232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122870187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. St. Onge, S.G. Franz, A. Puttlitz, A. Kalinoski, B. Johnson, B. El-Kareh
{"title":"Design of precision capacitors for analog applications","authors":"S. St. Onge, S.G. Franz, A. Puttlitz, A. Kalinoski, B. Johnson, B. El-Kareh","doi":"10.1109/ECTC.1992.204262","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204262","url":null,"abstract":"The authors describe and analyze two capacitors which are incorporated in a baseline BiCMOS technology without added process complexity. The first capacitor is formed between degenerated doped polysilicon and silicon. The second is formed between two degenerately doped polysilicon layers. In both structures, the insulator is a deposited or grown oxide. The sensitivity of the capacitor voltage coefficient to oxide thickness and surface dopant concentration is discussed theoretically and compared to measured data. The two capacitors are optimized to exhibit very low voltage coefficients.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126334594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Masaitis, A. Muller, R. Opila, L. Psota-Kelty, S. Daoud
{"title":"Characterization and reliability of electrolytic capacitors exposed to halogenated solvents","authors":"R. Masaitis, A. Muller, R. Opila, L. Psota-Kelty, S. Daoud","doi":"10.1109/ECTC.1992.204266","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204266","url":null,"abstract":"To determine the effect of exposure to halogenated solvents on electrolytic-capacitor lifetime, populations of these capacitors were exposed to accelerated testing. It is shown that halogenated solvents cause electrolytic capacitors to fail open at the anode. The electrolytic corrosion, which dissolves the passivating oxide layer on the anodically biased aluminum and exposes a clean aluminum surface, is the rate limiting step in the failures. Halogenated solvents then readily react with the aluminum surface and erode the electrode until the solvent is consumed. The increase in pressure inside the capacitor can cause the capacitor to vent, further accelerating failure. Accelerated life testing of one of the capacitor types considered suggests that it may fail at normal operating conditions in 2-3 years. Monitoring of capacitor characteristics during the accelerated life test shows that changes in these characteristic parameters cannot be used to predict failure.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126405297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Elastomeric sockets for chip carriers and MCMs","authors":"L.S. Buchoff","doi":"10.1109/ECTC.1992.204226","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204226","url":null,"abstract":"Sockets containing elastomeric elements have been successful in connecting very high density leadless chip packages and LGAs to PWBs (printed wiring boards). Connections are made by sandwiching the elements between the two mated substrates, producing a zero insertion force contact. The elastomer effectively seals out moisture and other degrading environments, ensuring long, reliable operation. The two elastomeric elements that are the most effective are the layered connectors and the metal-in-elastomer elements. These elements are described, and the development of sockets for MCMs (multichip modules) and chip carriers is described. Attention is given to test and burn-in sockets, permanent connections, and electronic package design.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127202572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Scotti, W. MacDonald, J. Gates, E. Ackerman, S. Wanuga, J. Komiak, D. Kasemset
{"title":"A 6-GHz lightwave transceiver module for microwave fiber-tic communications","authors":"R. Scotti, W. MacDonald, J. Gates, E. Ackerman, S. Wanuga, J. Komiak, D. Kasemset","doi":"10.1109/ECTC.1992.204303","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204303","url":null,"abstract":"A novel 6-GHz lightwave/microwave transceiver module has been demonstrated which combines AT&T's advanced lightwave packaging (ALP) technology with GE's monolithic microwave integrated circuit (MMIC) module technology. The optical transceiver module produced 11 dB of RF-to-RF gain over an octave bandwidth of 3-6 GHz. The ALP is miniaturized so that it may be integrated within a transmit, receive (T/R) module package or as a stand-alone small-size optical transceiver.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114900908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Subsystem optical interconnections using long-wavelength LD and singlemode-fiber arrays","authors":"A. Takai, H. Abe, T. Kato","doi":"10.1109/ECTC.1992.204193","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204193","url":null,"abstract":"Subsystem optical interconnections for lengths of over 100 m are proposed. Single-mode fiber (SMF) arrays and very-low-threshold-current long-wavelength laser diode (LD) arrays realize small-skew and error-free interconnections. The LD turn-on delay and receiver risetime and falltime (t/sub r//t/sub f/) skews are considered in addition to the electronic and fiber skews, and a total skew of less than 1.65 ns is obtained. It is shown that an SMF array with a skew of 2.1 ps/m is needed to obtain a small skew. The LD array can be coupled with an SMF array to give high signal-to-noise ratio and error-free transmission. Driving each LD at a modulation current of six times the threshold current results in an LD turn-on delay skew of less than 500 ps. Wideband preamplifiers with low feedback resistivity reduce receiver t/sub r//t/sub f/ skew. The total skew of 1.65 ns gives a transmission speed of less than 150 MB/s (150 Mb/s/ch*8 ch) through a 100-m fiber array.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123128068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Gold-Gold (Au-Au) thermocompression (TC) bonding of very large arrays","authors":"B.K. Kurman, S. Mita","doi":"10.1109/ECTC.1992.204311","DOIUrl":"https://doi.org/10.1109/ECTC.1992.204311","url":null,"abstract":"The authors demonstrate a technique, very large array bonding (VLAB), that extends Au-Au TC bonding from a single connection or tens of connections, to thousands or tens of thousands of connections over a large area in a single joining cycle. A description of a semi-isostatic gas pressure press developed for joining metal and/or metal/polymer arrays onto ceramic or silicon substrates is presented. Bond yields of 99.97% for metal/polyimide thin film arrays containing nearly 60000 contacts to pads on a 127-mm ceramic substrate have been achieved.<<ETX>>","PeriodicalId":125270,"journal":{"name":"1992 Proceedings 42nd Electronic Components & Technology Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125654922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}