7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era最新文献_第3页

Analytical dynamic power model for LUT based components 基于LUT组件的解析动态功率模型

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232957

Najoua Chalbi, Mohamed Boubaker, M. Hedi

引用次数: 6

Parameters estimation of ΣΔ modulators models using a combined optimization algorithm in MATLAB® environment 在MATLAB®环境下使用组合优化算法估计ΣΔ调制器模型的参数

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232972

R. Maghrebi, M. Masmoudi

引用次数: 0

A 250 μW 0.194 nV/rtHz Chopper-Stabilized instrumentation amplifier for MEMS gas sensor 用于MEMS气体传感器的250 μW 0.194 nV/rtHz斩波稳定仪表放大器

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232977

J. Nebhen, S. Meillére, M. Masmoudi, J. Seguin, H. Barthélemy, K. Aguir

引用次数: 3

Exploring SoPC technology and RTOS issues for industrial motor control 探讨工业电机控制的SoPC技术和RTOS问题

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232970

A. K. B. Salem, S. B. Othman, Moktar Bouain, S. B. Saoud

引用次数: 0

ALU based address generation for RAMs 基于ALU的ram地址生成

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232964

I. Voyiatzis, C. Efstathiou, S. Hamdioui, C. Sgouropoulou

引用次数: 4

Simulation-based multi-objective optimization of current conveyors: Performance evaluations 基于仿真的传送带多目标优化:性能评价

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232948

A. Sallem, B. Benhala, M. Kotti, M. Fakhfakh, A. Ahaitouf, M. Loulou

引用次数: 11

A novel architecture to reduce test time in march-based SRAM tests 在基于三月的SRAM测试中减少测试时间的新架构

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232963

I. Voyiatzis, C. Efstathiou, Y. Tsiatouhas, C. Sgouropoulou

引用次数: 1

New digital Pulse-Mode Neural Network based image denoising 基于数字脉冲模式神经网络的图像去噪

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232959

Amir Gargouri, M. Krid, D. Masmoudi

{"title":"New digital Pulse-Mode Neural Network based image denoising","authors":"Amir Gargouri, M. Krid, D. Masmoudi","doi":"10.1109/DTIS.2012.6232959","DOIUrl":"https://doi.org/10.1109/DTIS.2012.6232959","url":null,"abstract":"In this paper, we propose a new architecture of Pulse Mode Neural Network (PMNN) with very simple activation function. Pulse mode is gaining support in the field of hardware Neural Networks thanks to its higher density of integration. However, the complexity of the activation functions presents a drawback for hardware implementation of Neural Networks and limits its area of application. In this context, the main idea is to apply a new kind of activation function, simply generated by the product of two sigmoidal functions, which are very simple and already implemented in previous work. Details of important aspects concerning the hardware implementation are given. To verify the performance and capacity of the proposed design, we apply it for approximation of image denoising function. The filtered results are verified in terms of the Peak Signal to Noise Ratio (PSNR). Experimental results reveal that the proposed PMNN filter has a greater ability to recover the informative pixel intensities from the infected image with a recovery of 7.5 dB for Gaussian noise and 5.3 dB for Speckle noise. Besides, such results demonstrate the performance and efficiency of our Neural filter when compared to other conventional filtering techniques. The designed network is implemented on a field-programmable gate array (FPGA) platform and synthesis results are presented and discussed.","PeriodicalId":114829,"journal":{"name":"7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122604986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

On optimizing test cost for Wafer-to-Wafer 3D-stacked ICs 晶圆间3d堆叠集成电路测试成本优化研究

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232983

M. Taouil, S. Hamdioui

{"title":"On optimizing test cost for Wafer-to-Wafer 3D-stacked ICs","authors":"M. Taouil, S. Hamdioui","doi":"10.1109/DTIS.2012.6232983","DOIUrl":"https://doi.org/10.1109/DTIS.2012.6232983","url":null,"abstract":"The increasing demand for more sophisticated ICs with more functionality mostly was realized by downscaling and increasing the number of transistors. A technology that promises further increase of transistor density (in addition with heterogeneous integration, better performance and less power dissipation at a smaller footprint) is the three-dimensional stacked ICs (3D-SICs). Several stacking approaches are under development to manufacture such 3D-SICs. Wafer-to-Wafer (W2W) stacking seems the most favorable approach when high manufacturing throughput, thinned wafers and small die handling is required. However, efficient and optimal test approaches to satisfy the required quality are still subject to research. Each manufactured 3D-SIC undergoes a test and therefore optimizing test cost will have a large overall impact. This paper discusses test cost optimization for W2W 3D-SICs. It first introduces a framework covering different test flows for 3D W2W ICs. Test flows that include pre-bond tests can benefit from wafer matching; in wafer matching a software algorithm is used to increase the compound yield by stacking wafers with similar fault distributions. Subsequently, the paper proposes a cost model to evaluate and estimate the impact of test flows on the overall 3D-SIC cost. Our simulation results show that test flows with pre-bond testing in general significantly reduce the overall cost. These test flows benefit mostly from the yield increase due to wafer matching.","PeriodicalId":114829,"journal":{"name":"7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124879959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Mobile radio communication in aquatic environment 水生环境下的移动无线电通信

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232956

Mouna Aoun, Mohamed Amine Ben Farah, M. Samet, A. Kachouri

引用次数: 0