7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era最新文献_第4页

Improving IO test and system evaluation via data sharing 通过数据共享改进IO测试和系统评估

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232967

A. Meixner, S. Abdennadher

引用次数: 1

Modeling and design of a Folded Cascode bulk driven OTA 折叠Cascode批量驱动OTA的建模与设计

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232986

Intissar Toihria, T. Tixier

{"title":"Modeling and design of a Folded Cascode bulk driven OTA","authors":"Intissar Toihria, T. Tixier","doi":"10.1109/DTIS.2012.6232986","DOIUrl":"https://doi.org/10.1109/DTIS.2012.6232986","url":null,"abstract":"Analog circuit design is often based on a large number of simulations which strongly depends on the mastery of CAD tools and competence of the designer. In this context, the automated design of analog architectures becomes a necessity of design to solve the problem of simulation time. More importantly, accelerating the design cycle of the analog block, taking into account many constraints and finally formalizing the experience of analogiciens designers. In this paper we present a method for modeling the performance parameters of analog architectures, this is for the optimization of optimal sizing of transistors constituting the circuit to achieve the desired characteristics. This work is done following a modeling of the functioning of the Operational Amplifier using mathematical formulation software “Maxima”. The formulation is based on the SPICE level 1 model of the MOS transistor. Finally, the elaboration of the model is developed under MATLAB. The proposed method is presented and applied to the modeling and design of a Folded Cascode bulk driven OTA using a 0.35μm CMOS technology. Simulations with Cadence Spectrum are presented and compared with manual calculations and also to numerical calculations that have shown the effectiveness of the proposed methodology. Then, we determine the optimal parameters of the operational amplifier, which accord, maximum, to the desired specifications.","PeriodicalId":114829,"journal":{"name":"7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125480424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

The realization of a Neural Network controller for vehicle-type mobile robot navigation 车载移动机器人导航神经网络控制器的实现

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232945

Hanene Rouabah, C. Abdelmoula, M. Masmoudi

引用次数: 1

Performances of the AES design in 0.18μm CMOS technology 0.18μm CMOS工艺下AES设计性能分析

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232975

H. Mestiri, Mohsen Machhout, R. Tourki

引用次数: 10

ADS implementation of a new memristor based UWB chaotic generator ADS实现了一种新的基于忆阻器的超宽带混沌发生器

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232978

N. Rebhi, A. Kachouri, M. Samet

引用次数: 1

A mesochronous outfit for Network-on-Chip's interconnects retiming 一个用于片上网络互连重新定时的中同步装备

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232973

M. Zid, R. Tourki, A. Scandurra, Carlo Pistritto

{"title":"A mesochronous outfit for Network-on-Chip's interconnects retiming","authors":"M. Zid, R. Tourki, A. Scandurra, Carlo Pistritto","doi":"10.1109/DTIS.2012.6232973","DOIUrl":"https://doi.org/10.1109/DTIS.2012.6232973","url":null,"abstract":"Current VLSI systems-on-Chips (SoCs) integrate billions of transistors and are clocked with multi-gigahertz clock frequencies. As the geometrical dimensions of both devices and wires in theses systems become smaller, the internal communication performance between the SoC's blocks is heavily affected by the on-chip interconnect wire delays. In this paper, we propose a high efficient mesochronous outfit for network on chip (NoC) interconnects retiming. The proposed solution resolves the problem of clock skew and signal delays by using a delay locked loop (DLL) and a strobe signal to gauge the phase difference between two clock domains in a SoC. The asynchronism problem in the system is avoided by a data retiming accomplished by delaying signals with the mean of controllable delay buffers. The outfit foster alleviates the system's design complexity and results in a significant gain in their performances. The proposed device was implemented in 250 nm process technology and simulated for the worst case conditions using Tanner tool. Under a 3.3 V power supply and synched with a 800 MHz clock, the synchronizer consumes about 33.4 mW per bitline at room temperature.","PeriodicalId":114829,"journal":{"name":"7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115386885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of pass band filter in hybrid architecture planar/NRD waveguide integration technology 混合结构平面/NRD波导集成技术中的通带滤波器设计

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232974

H. Hanen, G. Ali

引用次数: 0

Virtual reality system on embedded platforms 嵌入式平台虚拟现实系统

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232969

T. Frikha, N. B. Amor, K. Loukil, M. Abid

引用次数: 1

On the optimal design of CC-based active filters 基于cc的有源滤波器的优化设计

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232947

A. Sallem, M. Fakhfakh, E. Tlelo-Cuautle, M. Loulou

引用次数: 1

A compact 32-bit AES design for embedded system 一种用于嵌入式系统的紧凑32位AES设计

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI: 10.1109/DTIS.2012.6232955

N. Benhadjyoussef, Mohsen Machhout, W. El Hadj Youssef, R. Tourki

引用次数: 6