7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era最新文献

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Architecture and HW/SW validation of nonlinear Border-Preserving Interpolator 非线性保边插值器的结构及软硬件验证
A. Boudabous, A. Atitallah, L. Khriji, N. Masmoudi
{"title":"Architecture and HW/SW validation of nonlinear Border-Preserving Interpolator","authors":"A. Boudabous, A. Atitallah, L. Khriji, N. Masmoudi","doi":"10.1109/DTIS.2012.6232968","DOIUrl":"https://doi.org/10.1109/DTIS.2012.6232968","url":null,"abstract":"In this paper, a new hardware implementation of the Border-Preserving Interpolator is presented. The object of this proposed work is to achieve significant run time performance using a hardware development board. It also demonstrates consistent image quality performance among a variety of images. This validation show that our implementation based on HW/SW design speeds up the interpolation process as well as preserving a high image quality.","PeriodicalId":114829,"journal":{"name":"7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115463892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Failure analysis of hot-electron effect on power RF N-LDMOS transistors 功率RF N-LDMOS晶体管热电子效应失效分析
M. A. Belaïd, M. Gares, K. Daoud, P. Eudeline
{"title":"Failure analysis of hot-electron effect on power RF N-LDMOS transistors","authors":"M. A. Belaïd, M. Gares, K. Daoud, P. Eudeline","doi":"10.1109/DTIS.2012.6232981","DOIUrl":"https://doi.org/10.1109/DTIS.2012.6232981","url":null,"abstract":"Comparative reliability of hot carrier induced electrical performance degradation is reported in power RF LDMOS transistors after novel methods for accelerated ageing tests with electrical and/or thermal stress. The effects of the reliability degradation mechanisms on the S-parameters and in turn on static and dynamic parameters are pointed out. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are studied by means of 2D ATLAS-SILVACO simulations. The RF performance degradation is explained by the transconductance and miller capacitance shifts, resulting from the interface state generation and trapped electrons, with a build up of negative charge at Si/SiO2 interface.","PeriodicalId":114829,"journal":{"name":"7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123031063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Realistic energy modeling of scheduling, interprocess-communication and context switch routines 调度、进程间通信和上下文切换例程的现实能量建模
B. Ouni, C. Belleudy, E. Senn
{"title":"Realistic energy modeling of scheduling, interprocess-communication and context switch routines","authors":"B. Ouni, C. Belleudy, E. Senn","doi":"10.1109/DTIS.2012.6232966","DOIUrl":"https://doi.org/10.1109/DTIS.2012.6232966","url":null,"abstract":"In this study, we introduce an approach about how to model energy and power consumption of embedded systems running operating system (OS). The embedded OS provides an abstraction layer to applicative tasks through system calls to exploit the hardware device resources. We interest in characterizing the energy overhead of the embedded OS services. The remainder of this article details the approaches used to determine energy and power overheads of a set of basic services of the embedded OS: scheduling, context switch and inter-process communication. We analyze the impact of a set of parameters like processor frequency and scheduling policy on the energy consumption. Then, we extract models and laws of these overheads. In our experiments, the hardware platform used is OMAP35x EVM board running Linux omap as operating system.","PeriodicalId":114829,"journal":{"name":"7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116737231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Towards non-uniformly controlled charge domain sample and hold for SDR receiver baseband stage 针对SDR接收机基带阶段的非均匀控制电荷域采样和保持
M. Ben-Romdhane, Oussama Rebai, M. Masmoudi, C. Rebai
{"title":"Towards non-uniformly controlled charge domain sample and hold for SDR receiver baseband stage","authors":"M. Ben-Romdhane, Oussama Rebai, M. Masmoudi, C. Rebai","doi":"10.1109/DTIS.2012.6232971","DOIUrl":"https://doi.org/10.1109/DTIS.2012.6232971","url":null,"abstract":"The time-quantized pseudorandom sampling (TQ-PRS) offers alias attenuation. The TQ-PRS-based baseband stage in a software defined radio (SDR) profit from this advantage to relax constraints on the analog-to-digital converter (ADC) and the anti-aliasing filter (AAF). However, the spectrum analysis of the TQ-PRS-controlled ADC experimental test results shows spurious replicas which are not present in simulation results. In this paper, the presented investigations show that a charge domain sample and hold circuit prior to the ADC can attenuate the spurious replicas with at least 7 dB. A solution to more attenuate the spurious replicas consists on a discrete-time switched-capacitor filter stage in charge domain.","PeriodicalId":114829,"journal":{"name":"7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131215902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Combiners based on CMOS inverters and application in RF transmitter for wireless sensors 基于CMOS逆变器的组合器及其在无线传感器射频发射机中的应用
H. Thabet, S. Meillére, M. Masmoudi, J. Seguin, H. Barthélemy, K. Aguir
{"title":"Combiners based on CMOS inverters and application in RF transmitter for wireless sensors","authors":"H. Thabet, S. Meillére, M. Masmoudi, J. Seguin, H. Barthélemy, K. Aguir","doi":"10.1109/DTIS.2012.6232982","DOIUrl":"https://doi.org/10.1109/DTIS.2012.6232982","url":null,"abstract":"A new Combiner architecture for direct conversion transmitter based on CMOS inverters only and operating in transconductance mode is presented in this paper. Typical applications of an adder and a subtractor of two small amplitude signals are proposed to illustrate the circuit capabilities. The proposed circuit operation has been acted from measurements with the HCC/HCF4069UB Hex Inverter from the SGS Thomson Microelectronics [1].","PeriodicalId":114829,"journal":{"name":"7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131384348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Ultra low power low noise amplifier design for 2.4 GHz applications 超低功耗低噪声放大器设计,适用于2.4 GHz应用
Amina Msolli, Mohsen Nasri, A. Helali, H. Maaref
{"title":"Ultra low power low noise amplifier design for 2.4 GHz applications","authors":"Amina Msolli, Mohsen Nasri, A. Helali, H. Maaref","doi":"10.1109/DTIS.2012.6232962","DOIUrl":"https://doi.org/10.1109/DTIS.2012.6232962","url":null,"abstract":"Requirements of Wireless Sensor Network application which are limited power, required energy and moderate performance has been forced the Wireless Sensor Network transceiver designers toward an adaptive transceiver structures. To address the above mentioned concerns, a low-noise amplifier integrated in 2.4 GHz, in 0.18 μm CMOS technology is developed. The proposed LNA can operate at 1.8 V supply voltage. The LNA provides a good gain of 17 dB, a noise figure of 0.01 dB, reverse isolation (S12) of -3 dB, input return loss (S11) of -15 dB and output return loss (S22) of -7 dB, while consuming only 7.2 Mw DC power.","PeriodicalId":114829,"journal":{"name":"7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127995619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
New concentric circular design of ESPAR antenna for DoAs estimation of highly correlated signals 用于高相关信号DoAs估计的ESPAR天线新设计
S. Akkar, F. Harabi, A. Gharsallah
{"title":"New concentric circular design of ESPAR antenna for DoAs estimation of highly correlated signals","authors":"S. Akkar, F. Harabi, A. Gharsallah","doi":"10.1109/DTIS.2012.6232980","DOIUrl":"https://doi.org/10.1109/DTIS.2012.6232980","url":null,"abstract":"In this paper, a new design of Electronically Steerable Parasitic Array Radiator (ESPAR) antennas is proposed for directions of arrival (DoAs) estimation of coherent sources by the well known ESPRIT algorithm. The Spatial Smoothing technique (SS) is adapted to this antennas shape to remove signals' coherence. The excellent performances of the uniform circular geometry are used to ensure accurate DoAs estimation in all the azimuth coverage. Simulation results show that the use of the spatial smoothing technique with the proposed ESPAR antenna shape improves DoAs estimation accuracy compared to the original ESPRIT algorithm for ESPAR antennas especially in highly correlated sources situations and prove the validity of our approach.","PeriodicalId":114829,"journal":{"name":"7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127336227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Petri nets framework for analyzing the communication behavior of TLM modules 用于分析TLM模块通信行为的Petri网框架
I. Bennour
{"title":"Petri nets framework for analyzing the communication behavior of TLM modules","authors":"I. Bennour","doi":"10.1109/DTIS.2012.6232987","DOIUrl":"https://doi.org/10.1109/DTIS.2012.6232987","url":null,"abstract":"Assembling a SoC using third party blocs is still an error-prone, labor-intensive and time-consuming process, due to a misunderstanding of the their communication behavior. Part of the solution consists of providing, conjointly with the simulation transaction level model (TLM), visible and formal models that help in understanding and exploring its implicit communication behavior. For this purpose we have proposed a set of Petri net models to descript a TLM module's communication. All models have been developed and validated using the colored Petri net tool CPN.","PeriodicalId":114829,"journal":{"name":"7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134022137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Test set embedding into low-power sequences based on a traveling salesman problem formulation 基于旅行推销员问题公式的测试集嵌入到低功率序列
I. Voyiatzis, C. Efstathiou, D. Magos, C. Sgouropoulou
{"title":"Test set embedding into low-power sequences based on a traveling salesman problem formulation","authors":"I. Voyiatzis, C. Efstathiou, D. Magos, C. Sgouropoulou","doi":"10.1109/DTIS.2012.6232965","DOIUrl":"https://doi.org/10.1109/DTIS.2012.6232965","url":null,"abstract":"Current trends in VLSI designs necessitate low power during both normal system operation and testing activity. Traditional Built-in Self Test (BIST) generators rise the power consumption during testing, necessitating the addition of low-power solutions to the arsenal of BIST pattern generators. In this paper, the utilization of gray codes is investigated as a low-power BIST solution; Experimental results indicate that the investigated generators can result into shorter lower-power BIST sequences, compared to previously proposed solutions.","PeriodicalId":114829,"journal":{"name":"7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128935164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impact of operating points on DVFS power management 工作点对DVFS电源管理的影响
J. Khan, S. Bilavarn, C. Belleudy
{"title":"Impact of operating points on DVFS power management","authors":"J. Khan, S. Bilavarn, C. Belleudy","doi":"10.1109/DTIS.2012.6232960","DOIUrl":"https://doi.org/10.1109/DTIS.2012.6232960","url":null,"abstract":"Dynamic voltage and frequency scaling (DVFS) techniques are commonly used for energy management in modern systems to reduce processor clock frequency and corresponding voltages. This reduces overall power and energy utilization. However the power levels associated with corresponding frequencies play an important role in effective DVFS based strategies, as in some cases energy utilization can actually be increased. We present a DVFS based power strategy dedicated to video processing with an application to an H.264 decoder. We analyze the effectiveness of this strategy using an ARM1176JZF-S hardware platform and a QEMU based virtual platform configured with models of ARM processors. Our results show that we can gain up to 57 % by choosing correct adaptation constraints. However, results also show that the efficiency of a DVFS strategy depends upon the characteristics of operating points (frequency/voltage couples). In particular, attention must be paid to the power level gap between consecutive frequencies, to compensate the increase in execution time resulting from frequency downscaling*.","PeriodicalId":114829,"journal":{"name":"7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114281121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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