Architecture and HW/SW validation of nonlinear Border-Preserving Interpolator

Abstract

In this paper, a new hardware implementation of the Border-Preserving Interpolator is presented. The object of this proposed work is to achieve significant run time performance using a hardware development board. It also demonstrates consistent image quality performance among a variety of images. This validation show that our implementation based on HW/SW design speeds up the interpolation process as well as preserving a high image quality.