一种用于嵌入式系统的紧凑32位AES设计

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI:10.1109/DTIS.2012.6232955

N. Benhadjyoussef, Mohsen Machhout, W. El Hadj Youssef, R. Tourki

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引用次数: 6

摘要

近年来，人们对嵌入式平台上数据交易的安全性进行了大量的研究。高级加密标准AES (Advanced Encryption Standard)被认为是数据加密/解密的候选算法之一。该标准的一个重要应用是智能卡上的加密。在本文中，我们描述了一个为Rijndael算法开发的32位架构，以加速内存减少的32位平台上的执行。利用FPGA器件xc5vfx70t-2ff1136-6，在303.364 MHz频率下实现了极低成本的375个被占用切片。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A compact 32-bit AES design for embedded system

Recently, much research has been conducted for security of data transactions on embedded platforms. Advanced Encryption Standard (AES) is considered as one of a candidate algorithm for data encryption/decryption. One important application of this standard is cryptography on smart cards. In this paper we describe a 32-bits architecture developed for Rijndael algorithm to accelerate execution on 32-bits platforms with reduced memory. Using the FPGA device xc5vfx70t-2ff1136-6, a very low-cost implementation of 375 occupied Slices is obtained under 303.364 MHz frequency.

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7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era

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