在基于三月的SRAM测试中减少测试时间的新架构

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Pub Date : 2012-05-16 DOI:10.1109/DTIS.2012.6232963

I. Voyiatzis, C. Efstathiou, Y. Tsiatouhas, C. Sgouropoulou

{"title":"在基于三月的SRAM测试中减少测试时间的新架构","authors":"I. Voyiatzis, C. Efstathiou, Y. Tsiatouhas, C. Sgouropoulou","doi":"10.1109/DTIS.2012.6232963","DOIUrl":null,"url":null,"abstract":"We present a scheme to reduce the test application time in memory march algorithm application by providing the capability to enable in parallel more than one output of the address decoder during write operations. The reduction in test time, depending on the march algorithm, ranges from 25% to 60%, while the hardware overhead increase for 1 Kbyte SRAM's is less than 2,5%.","PeriodicalId":114829,"journal":{"name":"7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A novel architecture to reduce test time in march-based SRAM tests\",\"authors\":\"I. Voyiatzis, C. Efstathiou, Y. Tsiatouhas, C. Sgouropoulou\",\"doi\":\"10.1109/DTIS.2012.6232963\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a scheme to reduce the test application time in memory march algorithm application by providing the capability to enable in parallel more than one output of the address decoder during write operations. The reduction in test time, depending on the march algorithm, ranges from 25% to 60%, while the hardware overhead increase for 1 Kbyte SRAM's is less than 2,5%.\",\"PeriodicalId\":114829,\"journal\":{\"name\":\"7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-05-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DTIS.2012.6232963\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DTIS.2012.6232963","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

我们提出了一种方案，通过提供在写操作期间并行启用多个地址解码器输出的能力来减少内存行军算法应用中的测试应用时间。根据行军算法的不同，测试时间的减少幅度从25%到60%不等，而1 Kbyte SRAM的硬件开销增加不到2.5%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A novel architecture to reduce test time in march-based SRAM tests

We present a scheme to reduce the test application time in memory march algorithm application by providing the capability to enable in parallel more than one output of the address decoder during write operations. The reduction in test time, depending on the march algorithm, ranges from 25% to 60%, while the hardware overhead increase for 1 Kbyte SRAM's is less than 2,5%.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era

自引率

0.00%

发文量