Analytical dynamic power model for LUT based components

Abstract

This paper presents fast field programmable gate array (FPGA) analytical dynamic power models for basic operators at the RTL (Register Transfer Level) level. The methodology is an adaptation of an existing incremental power estimation method for Look Up Table based components. The models are based on the frequency, the activity rate and the input precision by using the Xpower tool with a free glitching. We have validated our approach by using the Euclidean distance computing application. The results show that the estimate is even closer to the real value when we use mathematical models of IPs with combination operators and the average accuracy of the model is higher and the maximum reached average error is equal to 3.14%. The power model is verified by on board measurement bench based on a Virtex2Pro FPGA real environment.