A novel architecture to reduce test time in march-based SRAM tests

Abstract

We present a scheme to reduce the test application time in memory march algorithm application by providing the capability to enable in parallel more than one output of the address decoder during write operations. The reduction in test time, depending on the march algorithm, ranges from 25% to 60%, while the hardware overhead increase for 1 Kbyte SRAM's is less than 2,5%.