Advanced Electronic Materials最新文献

{"title":"Coexistence of Large Nernst Effect and Axis‐Dependent Conduction Polarity in Semimetal MoSi\u0000 2","authors":"Orest Pavlosiuk,Maciej J. Winiarski","doi":"10.1002/aelm.70563","DOIUrl":"https://doi.org/10.1002/aelm.70563","url":null,"abstract":"ABSTRACT Transverse thermoelectric phenomena are often considered as an alternative strategy for improving thermoelectric performance beyond standard longitudinal Seebeck response. Here, we show that the semimetallic compound is a rare example of a material in which transverse thermopower arises from two different mechanisms. In zero magnetic field, this response may originate from axis‐dependent conduction polarity (ADCP), which is confirmed in by the observation of Seebeck coefficients of opposite signs along two crystallographic directions, in agreement with theoretical predictions. The presence of ADCP is further reflected in Hall effect measurements performed along the same crystallographic directions. In applied magnetic field, a second mechanism becomes operative. The combination of nearly perfect charge carrier compensation, high carrier mobility and possibly phonon‐drag effect generates a pronounced Nernst thermopower and Nernst power factor ( and at  K and  T). As these characteristics are not unique to , our results expand the range of materials in which large Nernst effect and ADCP may coexist, providing new opportunities to optimize transverse thermoelectric performance.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"8 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148933183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multi-Vth IGZO FETs Enabled by Continuous-wave Laser Scanning Annealing for Low Thermal Budget 3D Integration","authors":"Jun-Hyeok Choi,&nbsp;Kiyung Kim,&nbsp;Hyeon-Seok Shin,&nbsp;Uigwan Shin,&nbsp;Byeong Gwan Kim,&nbsp;Jae Hyeon Jun,&nbsp;Joon Kim,&nbsp;Yoonyoung Chung,&nbsp;Byoung Hun Lee","doi":"10.1002/aelm.202500834","DOIUrl":"10.1002/aelm.202500834","url":null,"abstract":"<p>Indium-gallium-zinc-oxide (IGZO) field-effect transistors (FETs), owing to their excellent electrical performance and back-end-of-line (BEOL) compatibility, are promising candidates for logic applications. Although various techniques have been extensively investigated to enhance IGZO FET performance, these approaches typically fall short in offering precise and scalable threshold voltage (V_th) control. In this study, we demonstrate multi-V_th IGZO FETs using continuous-wave laser scanning annealing (CW-LSA), a localized annealing process that allows V_th to be precisely controlled without requiring additional process steps. The fabricated devices exhibit a high on/off current ratio (∼10⁸), steep subthreshold swing (&lt; 84 mV dec⁻¹), and near-zero V_th (∼0 V), rendering them well-suited for various logic circuit applications. By tuning laser power and scan speed, three distinct V_th values, i.e., 0.22, 0.42, and 0.62 V (low, standard, and high V_th, respectively), with excellent uniformity, are achieved on a single wafer (coefficient of variation between 2.17% and 6.61%). Moreover, the low thermal budget of the CW-LSA process is successfully confirmed by fabricating IGZO FETs on polyimide substrates. These results highlight CW-LSA as a scalable and BEOL-compatible technique for enabling energy-efficient multi-V_th logic circuits and for monolithic 3D system integration.</p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"12 17","pages":""},"PeriodicalIF":5.9,"publicationDate":"2026-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202500834","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148633704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Abrupt and Gradual Resistive Switching in Interface-Modified IGZO Memristors","authors":"Krishna Rudrapal,&nbsp;Christian Spieth,&nbsp;Michael Oehme,&nbsp;Kathrin Küster,&nbsp;Ulrich Starke,&nbsp;Alwin Daus","doi":"10.1002/aelm.70530","DOIUrl":"10.1002/aelm.70530","url":null,"abstract":"<p>Indium gallium zinc oxide (IGZO) is a well-established channel material for thin-film transistors and has also emerged as a promising active layer for memristor applications. Further, IGZO memristors can exhibit both abrupt and gradual switching behaviors, which offer enhanced adaptability for future memory and neuromorphic computing systems. In this study, we have systematically modulated the surface defect states in IGZO thin films through Ar-plasma and ultraviolet ozone (UV-O₃) treatments, and investigated their influence on the memristive switching characteristics in a W/IGZO/Pt device architecture. Notably, Ar-plasma enabled forming-free abrupt switching behavior, while UV-O₃ led to a transition to gradual switching. The devices were subjected to 10³ direct-current sweep cycles and 10⁴ s of retention testing. Especially the Ar-plasma and untreated reference devices showed stable behavior, while the UV-O₃ showed initial drifts in both measurements. Additionally, the absolute switching voltages of all samples are ≤1 V. These results demonstrate that the switching behavior of IGZO-based memristors can be effectively tuned through simple surface treatments while maintaining reliable device performance, underscoring the strong potential of IGZO as a versatile material for next-generation memristor technologies.</p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"12 17","pages":""},"PeriodicalIF":5.9,"publicationDate":"2026-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.70530","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148717626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Intrinsic Ferromagnetism and Surface Oxidation in Nb2FeC: Revealed by Synchrotron-Based X-Ray Spectro- and Microscopy","authors":"Sambhu Charan Das,&nbsp;Kuan-Hung Chen,&nbsp;Wei-Xuan Lin,&nbsp;Hsiao-Tsu Wang,&nbsp;Cheng-En Lee,&nbsp;Ping-Hung Yeh,&nbsp;Cheng-En Zhang,&nbsp;Chao-Hung Du,&nbsp;Jau-Wern Chiou,&nbsp;Huang-Ming Tsai,&nbsp;Kim Hsu,&nbsp;Chun-Chieh Wang,&nbsp;Jigang Zhou,&nbsp;Jian Wang,&nbsp;Sekhar Chandra Ray,&nbsp;Deepak Vishnu S. K.,&nbsp;Chun-Wei Chen,&nbsp;Way-Faung Pong","doi":"10.1002/aelm.70534","DOIUrl":"10.1002/aelm.70534","url":null,"abstract":"<p>A-site substitution in M_n+1AX_n (MAX) phases with transition metals carrying partially filled 3<i>d</i> orbitals offers a pathway to induce magnetism in otherwise nonmagnetic layered carbides/nitrides. Here, we investigate Nb₂FeC, obtained by replacing the nonmagnetic Al site in Nb₂AlC with Fe, using synchrotron-based spectroscopy and microscopy. Structural analysis confirms hexagonal <i>P6₃/mmc</i> phase with alternating Fe and Nb₂C layers along the <b><i>c</i></b>-axis. Surface-sensitive X-ray absorption reveals a thin Fe-oxide overlayer from ambient exposure, while Fe in the bulk reveals alloying-driven hybridization between Fe and Nb states. Magnetization measurements establish robust ferromagnetism with a Curie temperature near 283 K. Importantly, Fe <i>L</i>_3,2-edge Scanning Transmission X-ray Microscopy (STXM) combined with X-ray Magnetic Circular Dichroism (XMCD) directly demonstrates intrinsic bulk ferromagnetism, even though conventional surface-sensitive XMCD shows no signal. The STXM-XMCD dichroic response remains nearly unchanged across regions of varying thickness, indicating that ferromagnetic (FM) correlations are confined within the two-dimensional Fe layers and coupled only weakly across Nb₂C spacers. Thickness-dependent absorption spectra further reveal Fe─Nb hybridization, underscoring the role of A-site substitution in tuning magnetic interactions. These findings identify Nb₂FeC as a rare/near room-temperature FM MAX phase and highlight A-site engineering as a versatile strategy for designing layered magnetic carbides for spintronic applications.</p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"12 17","pages":""},"PeriodicalIF":5.9,"publicationDate":"2026-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.70534","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148768290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TWIN: Ternary Weight and Input Neural Network Accelerators Using an Experimentally Informed Ferroelectric Carbon Nanotube FET Compact Model","authors":"Mohammad Khaleqi Qaleh Jooq,&nbsp;Abdolah Amirany,&nbsp;Martin F. Sarott,&nbsp;Beatriz Noheda,&nbsp;Johanna van Gent González,&nbsp;Kian Jafari,&nbsp;Elham Heidari,&nbsp;Mostafa Rahimi Azghadi,&nbsp;Hamed Dalir,&nbsp;Saeed Afshar","doi":"10.1002/aelm.70560","DOIUrl":"10.1002/aelm.70560","url":null,"abstract":"<p>Artificial intelligence systems are increasingly embedded in daily life, but they face area and power constraints. Consequently, alternatives to binary architectures are being pursued. Ternary logic is one of those solutions that offers increased data density and enhanced computational speed. However, area overhead remains a major barrier to low-cost, energy-efficient ternary systems. To address these challenges, we design compact and energy-efficient ternary logic gates based on the simulated negative differential resistance behavior of an experimentally informed ferroelectric carbon nanotube field-effect transistor (FeCNTFET) compact model. A 10nm <span></span><math>\u0000 <semantics>\u0000 <mrow>\u0000 <mi>H</mi>\u0000 <msub>\u0000 <mi>f</mi>\u0000 <mrow>\u0000 <mn>0</mn>\u0000 <mrow>\u0000 <mo>.</mo>\u0000 <mn>25</mn>\u0000 </mrow>\u0000 </mrow>\u0000 </msub>\u0000 <mi>Z</mi>\u0000 <msub>\u0000 <mi>r</mi>\u0000 <mrow>\u0000 <mn>0</mn>\u0000 <mrow>\u0000 <mo>.</mo>\u0000 <mn>75</mn>\u0000 </mrow>\u0000 </mrow>\u0000 </msub>\u0000 <msub>\u0000 <mi>O</mi>\u0000 <mn>2</mn>\u0000 </msub>\u0000 </mrow>\u0000 <annotation>${rm {H}}{{rm {f}}_{{0}{rm {.25}}}}{rm {Z}}{{rm {r}}_{{0}{rm {.75}}}}{{rm {O}}_{2}}$</annotation>\u0000 </semantics></math> ferroelectric thin film on <span></span><math>\u0000 <semantics>\u0000 <mrow>\u0000 <mi>SrTi</mi>\u0000 <msub>\u0000 <mi>O</mi>\u0000 <mn>3</mn>\u0000 </msub>\u0000 </mrow>\u0000 <annotation>${rm {SrTi}}{{rm {O}}_{3}}$</annotation>\u0000 </semantics></math>(001) was experimentally fabricated and characterized, and the extracted ferroelectric parameters were incorporated into a Landau–Khalatnikov submodel coupled to a 3nm CNTFET compact model calibrated against previously reported experimental CNTFET data. Our results indicate that by using the compact ternary FeCNTFET-based arithmetic units, the proposed Ternary neural network (TNN) accelerators require 85% fewer unit-sized transistors and consume 72% less power than the 8-bit integer implementation, with accuracy reductions of 3.1% and 5.1% for MNIST and CIFAR-10, respectively. These results indicate the potential of the proposed FeCNTFET-based TNN accelerator for energy- and resource-constrained applications.</p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"12 17","pages":""},"PeriodicalIF":5.9,"publicationDate":"2026-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.70560","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148861049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Millisecond-Scale Relaxation in Metastable HZO Ferroelectric Capacitors for Bio-Inspired Temporal Computing","authors":"Luca Fehlings,&nbsp;Thomas Mikolajick,&nbsp;Beatriz Noheda,&nbsp;Erika Covi","doi":"10.1002/aelm.202500794","DOIUrl":"10.1002/aelm.202500794","url":null,"abstract":"<p>Depolarization effects in <span></span><math>\u0000 <semantics>\u0000 <msub>\u0000 <mi>HfO</mi>\u0000 <mn>2</mn>\u0000 </msub>\u0000 <annotation>${rm HfO}_2$</annotation>\u0000 </semantics></math>-based ferroelectric devices have gained significant interest for research on non-volatile memory applications. Understanding retention mechanisms enables device optimization for temporal and brain-inspired computing in hardware. This work presents a ferroelectric capacitor stack that shows a metastable <span></span><math>\u0000 <semantics>\u0000 <msub>\u0000 <mi>P</mi>\u0000 <mo>↑</mo>\u0000 </msub>\u0000 <annotation>$mathrm{P_uparrow }$</annotation>\u0000 </semantics></math> state that relaxes on a millisecond scale through a unique interface configuration. Electrical characterization demonstrates the device's capability for implementing tunable time constants in hardware, followed by investigation of the electronic mechanisms underlying observed retention times to facilitate modeling of retention processes in <span></span><math>\u0000 <semantics>\u0000 <msub>\u0000 <mi>HfO</mi>\u0000 <mn>2</mn>\u0000 </msub>\u0000 <annotation>${rm HfO}_2$</annotation>\u0000 </semantics></math>-based ferroelectric capacitors. Internal electric fields stabilize one polarization state, enabling unipolar operation with millisecond retention for the unstable polarization. The observed retention loss depends on both polarization state and programming conditions, allowing exploitation of multiple memory time-scales in a single device. The defective interface in the material stack provides insight into retention loss mechanisms and internal bias field origins in <span></span><math>\u0000 <semantics>\u0000 <msub>\u0000 <mi>HfO</mi>\u0000 <mn>2</mn>\u0000 </msub>\u0000 <annotation>${rm HfO}_2$</annotation>\u0000 </semantics></math>-based ferroelectric devices. These internal bias fields are related to interface composition, with oxygen vacancies identified as a possible source. The results demonstrate that <span></span><math>\u0000 <semantics>\u0000 <msub>\u0000 <mi>HfO</mi>\u0000 <mn>2</mn>\u0000 </msub>\u0000 <annotation>${rm HfO}_2$</annotation>\u0000 </semantics></math>-based ferroelectric devices offer an elegant solution for realizing tunable time constants in scaled memory devices, providing memory elements for brain-inspired temporal computing hardware.</p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"12 17","pages":""},"PeriodicalIF":5.9,"publicationDate":"2026-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202500794","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148459603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low Thermal Resistance Architectures for AlGaN-Based Semiconductor Devices","authors":"Kidus Guye,&nbsp;Davide Orlandini,&nbsp;Seungheon Shin,&nbsp;Andy Allerman,&nbsp;Damena Agonafer,&nbsp;Siddharth Rajan,&nbsp;Samuel Graham","doi":"10.1002/aelm.70524","DOIUrl":"10.1002/aelm.70524","url":null,"abstract":"<p>Next-generation high-power radio-frequency (RF) devices increasingly demand transistors that operate efficiently with high gain at high frequencies. High-aluminum-content ultrawide-bandgap (UWBG) AlGaN alloys have shown great potential for enabling such high-frequency RF technologies. However, the widespread adoption of AlGaN-based RF devices is limited by thermal-management challenges arising from the intrinsically low thermal conductivity of AlGaN, which leads to higher device thermal resistance for a given geometry compared to GaN RF devices. As a result, these next-generation devices are highly susceptible to self-heating. This study investigates the thermal behavior of UWBG AlGaN devices, focusing on the effects of AlGaN channel thickness, substrate technology, and high-k material integration on reducing device thermal resistance to enable high-power operation. Experimental results demonstrate a record-low thermal resistance of 3.96 <span></span><math>\u0000 <semantics>\u0000 <mrow>\u0000 <mi>mm</mi>\u0000 <mo>·</mo>\u0000 <mi>K</mi>\u0000 </mrow>\u0000 <annotation>${rm mm}cdot{rm K}$</annotation>\u0000 </semantics></math>/W when an AlN substrate is employed and the AlGaN channel thickness is reduced to 5 nm. These findings provide valuable insights into mitigating thermal limitations in UWBG devices through device-level engineering and the strategic integration of high-k materials.</p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"12 17","pages":""},"PeriodicalIF":5.9,"publicationDate":"2026-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.70524","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148729050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"MoS2/Graphene Floating-Gate Transistor Toward Non-Volatile Memory and High-Precision Synaptic Operations","authors":"Md. Ibrahim Ahmed,&nbsp;Sharnali Islam","doi":"10.1002/aelm.70519","DOIUrl":"10.1002/aelm.70519","url":null,"abstract":"<p>Molybdenum disulfide (<span></span><math>\u0000 <semantics>\u0000 <msub>\u0000 <mi>MoS</mi>\u0000 <mn>2</mn>\u0000 </msub>\u0000 <annotation>${rm MoS}_2$</annotation>\u0000 </semantics></math>) and graphene, as two significant members of the two-dimensional family, have garnered considerable attention for enhanced non-volatile memory (NVM) applications. Nonetheless, the synaptic behavior of the <span></span><math>\u0000 <semantics>\u0000 <msub>\u0000 <mi>MoS</mi>\u0000 <mn>2</mn>\u0000 </msub>\u0000 <annotation>${rm MoS}_2$</annotation>\u0000 </semantics></math>/graphene floating-gate structures is yet to be comprehensively validated. This study presents a <span></span><math>\u0000 <semantics>\u0000 <msub>\u0000 <mi>MoS</mi>\u0000 <mn>2</mn>\u0000 </msub>\u0000 <annotation>${rm MoS}_2$</annotation>\u0000 </semantics></math>/graphene floating gate transistor designed for logic switching, non-volatile memory, and neuromorphic applications. The implementation of a graphene Dirac-source contact enables the device to achieve a subthreshold slope of 25 mV/decade, stable p-type transistor operation, and a high ON/OFF current ratio of 10<span></span><math>\u0000 <semantics>\u0000 <msup>\u0000 <mrow></mrow>\u0000 <mn>10</mn>\u0000 </msup>\u0000 <annotation>$^{10}$</annotation>\u0000 </semantics></math> with sub-nanowatt power consumption. The programming–erasing time is approximately 11 ns, a memory window of 5.9 V, and a projected 10-year retention of 91%. Synaptic functionality is further demonstrated through potentiation–depotentiation behavior, short- and long-term plasticity, as well as spike-timing-dependent plasticity [STDP], offering a platform toward next-generation low-power logic devices, reliable non-volatile memory technologies, and neuromorphic computing systems.</p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"12 17","pages":""},"PeriodicalIF":5.9,"publicationDate":"2026-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.70519","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148853398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fundamental Challenges, Physical Implementations, and Integration Strategies for Ising Machines in Large-Scale Optimization Tasks","authors":"Hyunjun Lee,&nbsp;Joon Pyo Kim,&nbsp;Sanghyeon Kim","doi":"10.1002/aelm.202500682","DOIUrl":"10.1002/aelm.202500682","url":null,"abstract":"<p>Ising machines are specialized hardware solvers designed to solve computationally hard combinatorial optimization problems by finding ground states of the Ising model. As von Neumann architecture encounters fundamental bottlenecks in data movement, parallelism, and energy consumption, diverse physical implementations of Ising machines emerge as promising alternatives. This review comprehensively examines state-of-the-art Ising machine implementations across five major categories: digital complementary metal-oxide-semiconductor (CMOS) platforms employing various annealing strategies, analog CMOS architecture based on physical interactions, emerging device-based systems using coupled oscillators and probabilistic bits, coherent Ising machines leveraging photonic processes, and quantum approaches including both annealing and gate-based algorithms. Each platform provides unique advantages rooted in its underlying physics, yet all face core bottlenecks in scaling and connectivity. These limitations exacerbate issues in power efficiency, time-to-solution, stochasticity, and reliability. Building on this cross-platform analysis, monolithic three-dimensional (M3D) integration is introduced as an emerging design paradigm to overcome planar constraints through vertical functional partitioning. This approach outlines how M3D integration could relax scaling and connectivity bottlenecks and may eventually enable Ising machines to reach the scale and complexity required for large-scale real-world optimization problems.</p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"12 17","pages":""},"PeriodicalIF":5.9,"publicationDate":"2026-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202500682","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147466039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Twisted MoS2 Bilayers as Functional Elements in Memtransistors: Hysteresis, Optical Signatures, and Photocurrent Kinetics (Adv. Electron. Mater. 17/2026)","authors":"Vladislav Kurtash,&nbsp;Ilya Eliseyev,&nbsp;Valery Davydov,&nbsp;Heiko O. Jacobs,&nbsp;Jörg Pezoldt","doi":"10.1002/aelm.70577","DOIUrl":"https://doi.org/10.1002/aelm.70577","url":null,"abstract":"<p><b>Rational Control of Hysteresis</b></p><p>Twisted MoS₂ stacking forms a moiré superlattice that reshapes the local charge landscape and strengthens transistor hysteresis compared with regular stacking. The enlarged memory window supports synapse-like, analog state retention in CVD memtransistors, offering an additional structural parameter to tune neuromorphic device behavior without changing materials or circuit complexity. See Research Article e00716 by Vladislav Kurtash and co-workers for more details.\u0000\u0000 <figure>\u0000 <div><picture>\u0000 <source></source></picture><p></p>\u0000 </div>\u0000 </figure></p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"12 17","pages":""},"PeriodicalIF":5.9,"publicationDate":"2026-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.70577","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148943268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}