69th Device Research Conference最新文献_第5页

15 nm diameter InAs nanowire MOSFETs 直径15nm的InAs纳米线mosfet

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994403

A. Dey, C. Thelander, M. Borgstrom, B. Borg, E. Lind, L. Wernersson

引用次数: 0

RIE lag directional coupler based integrated InGaAsP/InP ring mode-locked laser 基于RIE滞后定向耦合器的集成InGaAsP/InP环形锁模激光器

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994524

J. Parker, P. Binetti, Y. Hung, E. Norberg, L. Coldren

引用次数: 2

Vertical organic field-effect transistor array fabrication based on laser holography lithography process 基于激光全息光刻工艺的垂直有机场效应晶体管阵列制造

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994432

Donghyun Kim, Yongtaek Hong

引用次数: 1

Ultra-thin compound semiconductor on insulator (XOI) for MOSFETs and TFETs 用于mosfet和tfet的超薄绝缘体上化合物半导体

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994400

R. Kapadia, K. Takei, A. C. Ford, Hui Fang, S. Chuang, M. Madsen, S. Krishna, A. Javey

引用次数: 0

Interface states at high- к /InGaAs interface: H2O vs. O3 based ALD dielectric 高氧/InGaAs界面的界面状态:H2O与O3基ALD介电体

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994443

H. Madan, D. Veksler, Y.T. Chen, J. Huang, N. Goel, G. Bersuker, S. Datta

引用次数: 5

High performance GaN-on-Si power switch: Role of substrate bias in device characteristics 高性能GaN-on-Si功率开关:衬底偏置在器件特性中的作用

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994508

R. Chu, D. Zehnder, B. Hughes, K. Boutros

引用次数: 18

Monolithically grown InxGa1−xAs nanowire on silicon tandem solar cells with high efficiency 在硅串联太阳能电池上单片生长的InxGa1−xAs纳米线具有高效率

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994434

J. Shin, K. Kim, Hefei Hu, Ki Jun Yu, J. Rogers, J. Zuo, Xiuling Li

引用次数: 0

Intrinsic DC operation and performance potential of 50nm gate length hydrogen-terminated diamond field effect transistors 50nm栅长氢端金刚石场效应晶体管的直流工作特性和性能潜力

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994454

D. Moran, O. Fox, H. McLelland, S. Russell, P. May

引用次数: 0

Vertically scaled 5 nm GaN channel enhancement-mode N-polar GaN MOS-HFET with 560 mS/mm gm and 0.76 Ω-mm Ron 垂直缩放5nm GaN通道增强模式n -极性GaN MOS-HFET, 560ms /mm gm和0.76 Ω-mm Ron

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.6086642

Uttam Singisett, M. Wong, J. Speck, U. Mishra

{"title":"Vertically scaled 5 nm GaN channel enhancement-mode N-polar GaN MOS-HFET with 560 mS/mm gm and 0.76 Ω-mm Ron","authors":"Uttam Singisett, M. Wong, J. Speck, U. Mishra","doi":"10.1109/DRC.2011.6086642","DOIUrl":"https://doi.org/10.1109/DRC.2011.6086642","url":null,"abstract":"N-polar GaN field-effect-transistors (FETs) have the potential advantage in scaling to sub-50nm gate lengths because of the confinement provided by the wide bandgap back-barrier. High-performance enhancement-mode (E-mode) N-polar GaN devices with self-aligned source/drain have recently been demonstrated with a current gain cut-off frequency (ft) of 120 GHz at a gate length of 70 nm [1]. Further scaling of the gate length to sub-50nm dimensions would require vertical scaling of the GaN channel thickness to 5 nm and the incorporation of a high-k gate dielectric in order to maintain a high aspect ratio, and a positive threshold voltage. The proximity of the surface to the 2-DEG in the ultra-scaled channels lead to surface depletion, and reduced mobility which increase the parasitic access resistance. This problem becomes critical in the E-mode devices because of the lower modulation doping compared to D-mode devices. We report here a self-aligned N-polar GaN FET with a 5-nm GaN channel and atomic later deposited (ALD) Al2O3 gate dielectric with a peak Id of 1.2 A/mm and peak gm of 560 mS/mm. The Ron of 0.76 Ω-mm for this device is the lowest reported for E-mode GaN FETs [ 2, 3, 4].","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"330 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116449511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fermi-level pinning at metal/antimonides interface and demonstration of antimonides-based metal S/D Schottky pMOSFETs 金属/锑化物界面的费米级钉钉及基于锑化物的金属S/D肖特基pmosfet的演示

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994457

Z. Yuan, A. Nainani, J. Lin, B. R. Bennett, J. B. Boos, M. Ancona, K. Saraswat

{"title":"Fermi-level pinning at metal/antimonides interface and demonstration of antimonides-based metal S/D Schottky pMOSFETs","authors":"Z. Yuan, A. Nainani, J. Lin, B. R. Bennett, J. B. Boos, M. Ancona, K. Saraswat","doi":"10.1109/DRC.2011.5994457","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994457","url":null,"abstract":"III–V semiconductors are considered as promising candidates to replace silicon as the channel material in future technology nodes for transistors [1]. III–V n-channel MOSFETs have been extensively studied [2–4], showing high electron mobility. However, one of the most critical challenges in realizing high performance III–V MOSFETs is the difficulties in source/drain (S/D) design including parasitic resistance due to low solubility and poor activation of dopant and the “source starvation” effect due to low density of states [5–6]. Annealing of implant damage after S/D ion-implantation is also more problematic in III–V's due to the presence of 2 or more atomic species vs. group IV semiconductors (Fig.1). Use of Schottky-barrier (SB) metal S/D is a promising strategy to overcome these limitations [7]. Meanwhile, for III–V based CMOS logic, achieving a high mobility pMOSFET in a III–V channel remains a challenge. Antimony (Sb) based compound semiconductors have the highest electron and hole mobilities amongst all III–V materials. Recently, high performance strained channel InGaSb pMOSFETs [8] have been demonstrated. In this paper, we study the metal contact to antimonides compound. Good metal contact formed on p-type material and current suppression on n-type samples is attributed to the Fermi-level pinning at metal/antimonide interface and charge-neutral level being near the valence band edge. Schottky-barrier S/D p-MOSFETs is proposed and experimentally demonstrated which combines an InxGa1−xSb channel for good hole transport with metal S/D for low access resistance.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"65 33-34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132866994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3