Vertically scaled 5 nm GaN channel enhancement-mode N-polar GaN MOS-HFET with 560 mS/mm gm and 0.76 Ω-mm Ron

Abstract

N-polar GaN field-effect-transistors (FETs) have the potential advantage in scaling to sub-50nm gate lengths because of the confinement provided by the wide bandgap back-barrier. High-performance enhancement-mode (E-mode) N-polar GaN devices with self-aligned source/drain have recently been demonstrated with a current gain cut-off frequency (ft) of 120 GHz at a gate length of 70 nm [1]. Further scaling of the gate length to sub-50nm dimensions would require vertical scaling of the GaN channel thickness to 5 nm and the incorporation of a high-k gate dielectric in order to maintain a high aspect ratio, and a positive threshold voltage. The proximity of the surface to the 2-DEG in the ultra-scaled channels lead to surface depletion, and reduced mobility which increase the parasitic access resistance. This problem becomes critical in the E-mode devices because of the lower modulation doping compared to D-mode devices. We report here a self-aligned N-polar GaN FET with a 5-nm GaN channel and atomic later deposited (ALD) Al2O3 gate dielectric with a peak Id of 1.2 A/mm and peak gm of 560 mS/mm. The Ron of 0.76 Ω-mm for this device is the lowest reported for E-mode GaN FETs [ 2, 3, 4].