{"title":"Validation of module assembly physical models","authors":"R. Iannuzzelli","doi":"10.1109/ECTC.1990.122318","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122318","url":null,"abstract":"Some typical models used in the assembly of electronic modules are presented along with data establishing the validity of these models. Six cases are examined: two cases of PTH/PWB (plated-through-hole/printed wiring board) model validation: SMT (surface mount technology) reliability prediction using the matrix creep method; prediction of creep rupture times of SMT butt joints; PGA (pin grid array) cracking; and prediction of PWB deflection during BON (bed-of-nails) testing.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126809382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Tanaka, M. Okamoto, M. Oohashi, H. Arakawa, K. Yamada
{"title":"Low thermal resistance AlN PGA with low inductance of power lines","authors":"A. Tanaka, M. Okamoto, M. Oohashi, H. Arakawa, K. Yamada","doi":"10.1109/ECTC.1990.122210","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122210","url":null,"abstract":"A low-thermal-resistance and high-speed pin-grid-array (PGA) package with low-inductance power lines was proposed, and its feasibility was confirmed. To obtain low-inductance power lines, the wiring system in the package kept power-line layers and signal-line layers separate. Low inductance of power lines was realized by using conductive layers with a large area in an aluminium nitride (AlN) substrate and arranging the power pins just under the silicon chips. A high signal-propagation speed was realized by sandwiching radial signal lines between low-dielectric-constant polyimide layers. To obtain low thermal resistance, a silicon chip was soldered onto the metallized AlN ceramic substrate. High thermal conductivity of AlN ceramics and the arrangement of pins on the AlN substrate surface opposite the side of the silicon chip resulted in low thermal resistance of the package. The package on the printed wiring board had a thermal resistance of 3.0 degrees C/W at an air velocity of 1 m/s using a 14-mm-high aluminium cooling heat sink. The self-inductance of the power lines was 1.4 nH in the package substrate without pins and bonding wires.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125153223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Comparison of predicted and measured lead stiffnesses of surface mounted packages","authors":"W. Jahsman, P. Jain","doi":"10.1109/ECTC.1990.122300","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122300","url":null,"abstract":"A comparison was made of predicted and measured values of lead stiffness for selected surface-mounted packages. Excellent agreement was found in all cases: 68- and 44-lead plastic leaded chip carriers (PLCCs) and cerquads (pressed ceramic quad flat pack); and 100-lead plastic quad flat packs (PQFPs). Predictions were based on the 3D elastic beam finite-element option of ANSYS, with lead geometries taken from design drawings and lead elastic properties from material specifications. Measured values were taken from straddle board test data. In these tests, the board is straddled on both sides by packages surface mounted by only their lateral or transverse leads so that lateral and transverse bending effects can be measured independently. The results point out the importance of low stiffness lead design in minimizing solder-joint deformation.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121975108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Damage in silicon caused by magnetron ion etching and its recovery effect","authors":"M. Hirai, H. Iwakuro, J. Ohno, T. Kuroda","doi":"10.1109/ECTC.1990.122263","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122263","url":null,"abstract":"Damage in silicon exposed to an MIE (magnetron ion etching) plasma has been investigated. The damage was characterized by Schottky barrier height measurements using Al/n-Si diodes. The depths of the damaged layer are determined as a function of RF power. It is found that the damaged layer at an RF power of 2 kW (self-bias: 270 V) is about 12 nm, and that the damage depths correlate with the self-bias voltage, that is, the energy of ions impinging on the Si surface during plasma exposure. Several methods for removal of the damaged layer were examined. It was found that the damaged layer can be removed by a wet Si etching.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122518994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Ku, M. J. Burns, B. Dean, T. F. Eltringham, F. Nash
{"title":"Reliability assurance of laser-fiber coupling in an undersea lightwave package","authors":"R. Ku, M. J. Burns, B. Dean, T. F. Eltringham, F. Nash","doi":"10.1109/ECTC.1990.122164","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122164","url":null,"abstract":"Reliability assurance of a laser package for undersea lightwave communication systems is discussed. The difficulty in assuring long life on recent-technology components such as a laser package is the lack of extensive experience with failure modes. For this reason, an extensive testing program was conducted to detect and assess the possibility of failure of the package in the lightwave system. The reliability methodology consists of four parts: (1) direct low-temperature aging, (2) high-temperature accelerated aging, (3) accumulation of device hours, and (4) environmental-mechanical overstress testing to destruction. Results show a more than adequate margin against failure over the 27-yr service life.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124975902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new high temperature multilayer capacitor with acrylate dielectrics","authors":"A. Yializis, G. L. Powers, D. Shaw","doi":"10.1109/ECTC.1990.122201","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122201","url":null,"abstract":"A capacitor technology that makes use of vacuum-deposited electron-beam cross-linked acrylate materials has been developed. Polymer multilayer monolithic capacitors are produced by a continuous high-speed vacuum process. The polymer dielectric is formed by flash-evaporating an acrylate monomer material onto a rotating drum and then cross-linking it by electron-beam irradiation. The resulting polymer is thermally stable at temperatures in excess of 300 degrees C. The dielectric films are pinhole-free, with stable electrical properties. The capacitor electrodes are vapor-deposited aluminium and are thin enough to allow the capacitor to self-heal. The number of layers typically varies between 1000 and 5000 and the dielectric thickness between 0.3 and 1.0 mu m. The low dielectric thickness results in capacitor chips with high volumetric efficiency that can be surface mounted by conventional soldering techniques. An overview of the vacuum process, chip cutting, termination, packaging, electrical characteristics, and general test methodology is given here.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"267 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122157223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. A. Lesk, R.E. Thomas, G. Hawkins, T. Remmel, J. Rugg
{"title":"Progression of damage caused by temperature cycling on a large die in a molded plastic package","authors":"I. A. Lesk, R.E. Thomas, G. Hawkins, T. Remmel, J. Rugg","doi":"10.1109/ECTC.1990.122282","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122282","url":null,"abstract":"Large silicon chips in molded plastic packages suffer physical damage to top-surface regions when subjected to repetitive thermal excursions. It is shown that a delamination between the molding compound and the die surface, progressing inward from a crack in the molding compound at a die corner, can enter an aluminum film through a crack in the passivation glass at an edge, travel through the metal, and exit at the opposite edge. This permits migration of glass and metal inward from corner regions. It is pointed out that reduced susceptibility to this effect may be obtained through the use of tougher metal, thicker passivation glass in lower metal edge corners, and tougher glass. A silicon integrated circuit chip approximately 250*290 mils in a 52-lead PLCC (plastic leaded chip carrier) was used as a test vehicle. Temperature and thermal shock cycling, from as low as -65 degrees C to +150 degrees C and for as many as 2000 cycles was performed.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"61 25","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120816821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Trends in laser packaging","authors":"D. Alles","doi":"10.1109/ECTC.1990.122187","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122187","url":null,"abstract":"The author reviews the advances in the electrical, mechanical, and optical design of laser packages over the past few years and indicates the current state of the art. The examples focus on how changes in the design and materials have resulted in performance improvements and cost reductions. A list of desirable future laser packages is presented.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"48 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120971394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"New screen-printable polyimide for IC devices","authors":"H. Nishizawa, K. Suzuki, T. Kikuchi, H. Satou","doi":"10.1109/ECTC.1990.122268","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122268","url":null,"abstract":"In order to develop a screen-printable polyimide paste, the structures, properties, and ratios of three major paste components (filler, binder, and solvent) were studied, and a film-forming strategy was established. This strategy comprises a novel type of polyimide particle filler, which can be dissolved in the binder and the solvent under the curing condition. A screen-printable polyimide paste was developed using this strategy. This paste gives uniform film with better mechanical properties than conventional polyimide paste, which comprises an insoluble polyimide particle filler. The effect of the solubility parameter of the solvent on mask swelling and moisture resistance was also examined. It was also examined. It was found that a lactone with a solubility parameter value of 18 approximately 20 (MJ/m/sup 3/)/sup 1/2/ is suitable as a paste solvent. The paste affords uniform pinhole-free polyimide films with good mechanical properties. As the mask swelling is low, the lifetime of stencil is longer than that of conventional pastes.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134432114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reliability improvements in solder bump processing for flip chips","authors":"M. Warrior","doi":"10.1109/ECTC.1990.122229","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122229","url":null,"abstract":"A plated solder-bump process used for the manufacture of high-reliability flip chips is described. Characterization work done to improve the process manufacturability and the resulting product reliability gains are reviewed. Two detailed studies of the thin-film deposition conditions and the Cu pedestal plating parameters are described. Recommendations implemented as a result of these studies have reduced the bump-interconnect-failure level from a defect rate of approximately 500 p.p.m. to <10 p.p.m. Excellent temperature cycling performance of assembled hybrids was obtained. The process has been used in high-volume production to manufacture ICs used in automobiles (under-hood application). In process capability has improved from a C/sub p/<1 to C/sub p/>1.5. This work highlights the need and the benefits of detailed characterization, which results in more robust manufacturing processes and eventually in more reliable product performance.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132757605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}