{"title":"倒装芯片焊料凸点加工的可靠性改进","authors":"M. Warrior","doi":"10.1109/ECTC.1990.122229","DOIUrl":null,"url":null,"abstract":"A plated solder-bump process used for the manufacture of high-reliability flip chips is described. Characterization work done to improve the process manufacturability and the resulting product reliability gains are reviewed. Two detailed studies of the thin-film deposition conditions and the Cu pedestal plating parameters are described. Recommendations implemented as a result of these studies have reduced the bump-interconnect-failure level from a defect rate of approximately 500 p.p.m. to <10 p.p.m. Excellent temperature cycling performance of assembled hybrids was obtained. The process has been used in high-volume production to manufacture ICs used in automobiles (under-hood application). In process capability has improved from a C/sub p/<1 to C/sub p/>1.5. This work highlights the need and the benefits of detailed characterization, which results in more robust manufacturing processes and eventually in more reliable product performance.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"Reliability improvements in solder bump processing for flip chips\",\"authors\":\"M. Warrior\",\"doi\":\"10.1109/ECTC.1990.122229\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A plated solder-bump process used for the manufacture of high-reliability flip chips is described. Characterization work done to improve the process manufacturability and the resulting product reliability gains are reviewed. Two detailed studies of the thin-film deposition conditions and the Cu pedestal plating parameters are described. Recommendations implemented as a result of these studies have reduced the bump-interconnect-failure level from a defect rate of approximately 500 p.p.m. to <10 p.p.m. Excellent temperature cycling performance of assembled hybrids was obtained. The process has been used in high-volume production to manufacture ICs used in automobiles (under-hood application). In process capability has improved from a C/sub p/<1 to C/sub p/>1.5. This work highlights the need and the benefits of detailed characterization, which results in more robust manufacturing processes and eventually in more reliable product performance.<<ETX>>\",\"PeriodicalId\":102875,\"journal\":{\"name\":\"40th Conference Proceedings on Electronic Components and Technology\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-05-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"40th Conference Proceedings on Electronic Components and Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECTC.1990.122229\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"40th Conference Proceedings on Electronic Components and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.1990.122229","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reliability improvements in solder bump processing for flip chips
A plated solder-bump process used for the manufacture of high-reliability flip chips is described. Characterization work done to improve the process manufacturability and the resulting product reliability gains are reviewed. Two detailed studies of the thin-film deposition conditions and the Cu pedestal plating parameters are described. Recommendations implemented as a result of these studies have reduced the bump-interconnect-failure level from a defect rate of approximately 500 p.p.m. to <10 p.p.m. Excellent temperature cycling performance of assembled hybrids was obtained. The process has been used in high-volume production to manufacture ICs used in automobiles (under-hood application). In process capability has improved from a C/sub p/<1 to C/sub p/>1.5. This work highlights the need and the benefits of detailed characterization, which results in more robust manufacturing processes and eventually in more reliable product performance.<>