{"title":"Grain boundary sliding in surface mount solders during thermal cycling","authors":"S. Lee, D. Stone","doi":"10.1109/ECTC.1990.122233","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122233","url":null,"abstract":"The growth of fatigue cracks in near-eutectic, surface-mount solder joints during cyclic, thermal displacement-controlled loading is reported. Ceramic leadless chip carriers (LLCC) are subjected to thermal fatigue with a frequency of 1/hr and over two ranges of temperature: -36 degrees C to 125 degrees C and -20 degrees C to 75 degrees C. Surfaces and cross-sections of the solder joints are inspected using scanning electron microscopy. Individual grains (colonies of lamellae and globulae) are found to slide relative to one another during thermal cycling. Sliding causes fatigue cracks to initiate at the surface.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116468814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of HWSI multichip modules for quick prototyping and manufacturing","authors":"Y. Lee","doi":"10.1109/ECTC.1990.122247","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122247","url":null,"abstract":"The constraints imposed by the semicustom approach on multichip module designs are studied using a design case that interconnects a 144-input/output (I/O) microprocessor and four memory chips. The results show that semicustom hybrid wafer-scale-integration (HWSI) has enough real estate for complex designs even with the constraints on interconnection: a low inductance level (<0.2 nH) per power/ground (P/G) connection, even with an additional connection from a solder bump to a near thermal via; and alternative thermal management schemes to replace the ineffective thermal paths using solder bumps and thermal vias. These schemes use a custom-designed standard substrate for high-power chips, an alternative thermal path having enhanced gap conduction, or a compact immersion cooling design.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122591168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The performance and reliability of a new plated copper technology on ceramic","authors":"J. Fudala, M. Beke","doi":"10.1109/ECTC.1990.122324","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122324","url":null,"abstract":"A plated copper-on-ceramic technology that can be characterized as a ceramic PC (printed circuit) board is described. Adhesion of the plated copper on 96% alumina, 99.5% alumina, beryllium oxide, and aluminum nitrate was evaluated using a peel test method. The plated copper technology is shown to surpass previous plated copper processes in performance and reliability.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116326336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Laser/infrared evaluation of TAB innerlead bond integrity","authors":"Hongbee Teoh, Michael McGearyt, Jamin Ling","doi":"10.1109/ECTC.1990.122227","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122227","url":null,"abstract":"The feasibility of using laser/infrared technology as a noncontact and nondestructive inspection technique to assess tape automated bonded (TAB) inner-lead bond integrity was studied. Chip-on-tape samples with well-bonded inner leads and opens or lifted leads were evaluated. The peak thermal signals obtained during thermal decay after the laser was shut off were evaluated. For a given laser power and exposure time, good bonds and opens generated distinctly different infrared (IR) signatures during thermal decay. Typically, good bonds emitted peak amplitudes which were nominally two to five times lower than those for opens. These were attributed to the superior thermal dissipation properties of well-bonded interconnects as well as to the IR detector configuration in the inspector system. The IR signal modulations observed for well-bonded samples could be explained by the thermal mass/conductance variation associated with circuit metallization patterns on the silicon chip. The results showed that the technique investigated in this study could be adapted as an inprocess inspection scheme for detection of opens or lifted leads. However, refinements are still needed to improve the technique's capability.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"254 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126156993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. T. Panousis, J. F. Prosser, A. T. Wang, Y.N. Yong
{"title":"Strength and reliability of ceramic modules soldered to flexible cables","authors":"N. T. Panousis, J. F. Prosser, A. T. Wang, Y.N. Yong","doi":"10.1109/ECTC.1990.122217","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122217","url":null,"abstract":"The strength and reliability of soldered interconnections between module pins and flexible cables are discussed. A quantitative measure of the strength of the connection is described. Individual pins were mechanically tested by measuring the force required to push them through the cable, and force and failure mode were recorded. The push-through test was used to determine optimum solder volume for maximum initial strength and to measure degradation following exposure to environmental stresses. The first reliability stress was to store units at constant elevated temperature of 80, 100, and 125 degrees C for up to 8500 h. Analysis of these results was done with a nonlinear regression model. For the dominant mode, the results of this model are: PS/sub i/(t,T)=3.05-58*exp(-2629/T)*t/sup 0.38/+ epsilon /sub i/, where PS(t,T) is the push-through strength as a function of time, t, and Kelvin temperature, T. epsilon /sub i/ represents the random part and is distributed normally with 0 mean. These results give an effective activation energy of 0.6 eV. The second reliability test was to thermally cycle units between -40 and +100 degrees C for up to 1000 cycles. There was no degradation. A simple first-order estimate indicates that this is equivalent to about five lifetimes.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127477644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Relation between inner voids of plastic IC packages and non-Newtonian flow characteristics of resin encapsulant","authors":"S. Ichimura, K. Kinashi, T. Urano","doi":"10.1109/ECTC.1990.122255","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122255","url":null,"abstract":"The relationship between the flow characteristics of resin encapsulant an the number of inner voids in a plastic IC package was investigated. The number of inner voids decreased as the average transfer pressure rose. This indicated that the higher the viscosity of resin encapsulant in the molding die, the fewer the inner voids. However, the spiral flow (EMMI-1-66 standard), a general measure of resin encapsulant flow characteristics, is not proportional to the number of inner voids. This may be because resin encapsulant has non-Newtonian flow characteristics which change the viscosity with share rate. In comparison with the shear rate of an actual molding die, which is as low as 1 to 100/s in a runner or cavity, the shear rate of a molding die with spiral flow is as large as 100 to 1000/s. The viscosities in the low shear rate range were measured to get a good proportionality with the number of voids. In order to make the viscosity of the resin encapsulant higher in the low shear rate range, it is advisable to use fine filler or silicone flexibilizer.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"44 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126992902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Fujita, S. Oomi, K. Toyozawa, S. Minamide, T. Maeda
{"title":"Development of ultra-thin surface mounting IC package (0.8 mm thick TQFP)","authors":"K. Fujita, S. Oomi, K. Toyozawa, S. Minamide, T. Maeda","doi":"10.1109/ECTC.1990.122206","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122206","url":null,"abstract":"A TQFP (thin quad flat package) with a package size of 10*10 mm and a maximum package thickness of 0.8 mm has been developed to meet the need for lower profiles in surface-mounting packages. For a package thickness of 1.0 mm, the conventional lead-frame thickness and chip thickness are sufficient. However, when the package thickness is reduced to 0.8 mm, a reduction in at least one of the conventional thicknesses is absolutely essential. Therefore, by reducing the thickness of only part of the die-pad portion of the lead frame through the use of chemical etching to approximately 1/2 to 2/3, the resin thickness above the chip and below the die pad is ensured. A low-loop wire bond with a maximum of 0.14 mm was achieved by optimizing the wire material and wire-bond conditions. Ultrathin molding was achieved by improving the fluid characteristics of the resin and by ensuring the resin-fluid balance within the cavity. Package cracking and degraded moisture resistance were evaluated using a 4-Mbit mask ROM. After subjecting it to 85 degrees C and 75% RH for 72 h, no problems were noticed while soldering at 240 degrees C maximum with infrared reflow.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130726417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Silicones with improved thermal conductivity for thermal management in electronic packaging","authors":"A. L. Peterson","doi":"10.1109/ECTC.1990.122251","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122251","url":null,"abstract":"The design, use, and application of thermal compounds in popular electronic packages are described. Typical properties of silicones are addressed, including the differences between thermally conductive silicone greases, gels, and adhesives. Recent trends in electronic-packaging thermal-management techniques are also covered. Specific attention is given to multi-chip modules utilizing thermal compounds for heat removal through the top of the flip chip. The key properties of highly thermally conductive materials are highlighted. These areas include the selection of filler type, filler packing, and total filler loading. The properties of a thermal compound developed for flip-chip application are explained in detail, and attention is given to how the above areas have been optimized in this product. It is concluded that the proper selection and use of thermally conductive silicones, as presently described, can greatly enhance the performance of many electronic packages.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132164045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Production of MCP chip carriers","authors":"M. E. Williams","doi":"10.1109/ECTC.1990.122222","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122222","url":null,"abstract":"Full-scale production of metallized ceramic polyimide (MCP) chip carriers has been practiced for several years by IBM. The MCP package includes two layers of circuitry that are electrically isolated except for vias through a polyimide dielectric layer. This circuitry/polyimide/circuitry sandwich is formed on top of an alumina ceramic base by several passes of photolithographic processing. Connection to the card is provided by pins that go through the ceramic package and into the card, and connection to the chip is provided by controlled collapse chip connection (C4) solder joints. The product construction, performance advantages, and future modifications are described.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134173132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Tsunashima, A. Okuno, N. Oyama, T. Hirakawa, K. Nishimura
{"title":"An aramid/epoxy substrates increased the facility of rigid-flexible substrates for high performance use","authors":"E. Tsunashima, A. Okuno, N. Oyama, T. Hirakawa, K. Nishimura","doi":"10.1109/ECTC.1990.122296","DOIUrl":"https://doi.org/10.1109/ECTC.1990.122296","url":null,"abstract":"A material has been developed for fabricating rigid-flexible printed boards. The material includes copper-clad laminates (TL-01) and prepregs (ET-100) consisting of a recently developed aramid paper made of an aramid fiber from poly-paraphenylene 3,4' diphenilether terephthalamid (PPDETA) as a reinforcement, and a sophisticated epoxy resin system having high affinity to an aramid fiber as an impregnant. The dimensional stability of the multilayer system has been shown to surpass that of the conventional lamination system of FR-4, polyimide films, and acrylic adhesives. A flexural fatigue test on the flexible printed wiring has been carried out, and the flexible material revealed a higher flexibility than FR-4. Copper migration has been observed after full absorption of moisture by a pressure cooker test (PCT). TL-01 has shown an excellent resistance to migration for more than 50 h, while polyimide film with an acrylic adhesive has shown a heavy migration. It is concluded that this material may be useful for advanced rigid-flex multilayer printed boards suitable for surface mount technologies.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131688575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}