IEEE Transactions on Signal and Power Integrity最新文献_第7页

Immunity Testing of Mixed Signal Electronics Against Power Supply Disturbances in the Frequency Range From 10 kHz To 5 MHz 混合信号电子器件在10kHz至5MHz频率范围内对电源干扰的抗扰度测试

IEEE Transactions on Signal and Power Integrity Pub Date : 2022-12-01 DOI: 10.1109/TSIPI.2022.3225511

Federico Sordi;Leonardo Vignoli;Lorenzo Capineri;Carlo Carobbi

{"title":"Immunity Testing of Mixed Signal Electronics Against Power Supply Disturbances in the Frequency Range From 10 kHz To 5 MHz","authors":"Federico Sordi;Leonardo Vignoli;Lorenzo Capineri;Carlo Carobbi","doi":"10.1109/TSIPI.2022.3225511","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3225511","url":null,"abstract":"A method is presented to test the immunity of mixed signal (digital and analog) electronics to power supply disturbances in the frequency range between 10 and 5 MHz, as those originating from switched mode power supplies. An example of application of the method to a serializer/deserializer integrated circuit is illustrated. For these electronic devices, the power supply noise can critically affect performance. The SerDes is hosted by an evaluation board supplied by an external power module (PM). An adhoc disturbance source and coupling/Decoupling network (CDN) have been designed to couple a disturbance of significant amplitude to the power supply of the evaluation board while decoupling it from the power module (PM). The radiofrequency mpedance of the bypass network of the evaluation board has been considered for the design of both the disturbance source and the CDN. Details about the architecture and operation of the high-current, broadband and linear power amplifier used for disturbance generation are provided, along with component selection and verification of the CDN. The practical implementation of the test, including a feedback control loop capable of generating the specified disturbance level over the frequency range of interest, is described. Finally, test results are reported in terms of the SerDes bit error rate degradation as a function of disturbance amplitude and frequency.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"170-178"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Uncertainty Quantification of Signal Integrity Analysis for Neuromorphic Chips 神经形态芯片信号完整性分析的不确定度量化

IEEE Transactions on Signal and Power Integrity Pub Date : 2022-11-16 DOI: 10.1109/TSIPI.2022.3222122

Hanzhi Ma;Da Li;Tuomin Tao;Xingjian Shangguan;En-Xiao Liu;Jose Schutt-Aine;Andreas C. Cangellaris;Er-Ping Li

引用次数: 1

Phase Noise Analysis of Clock Generator by Using Phase Noise Sensitivity 利用相位噪声灵敏度分析时钟发生器的相位噪声

IEEE Transactions on Signal and Power Integrity Pub Date : 2022-11-16 DOI: 10.1109/TSIPI.2022.3222747

Yuanzhuo Liu;Yuandong Guo;Chaofeng Li;Siqi Bai;Bichen Chen;Srinivas Venkataraman;Xu Wang;Jun Fan;DongHyun Kim

{"title":"Phase Noise Analysis of Clock Generator by Using Phase Noise Sensitivity","authors":"Yuanzhuo Liu;Yuandong Guo;Chaofeng Li;Siqi Bai;Bichen Chen;Srinivas Venkataraman;Xu Wang;Jun Fan;DongHyun Kim","doi":"10.1109/TSIPI.2022.3222747","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3222747","url":null,"abstract":"Phase noise represents signal instabilities in the frequency domain and is assessed through power measurements at various offsets from the carrier frequency. Herein, the phase noise of a clock generator is analyzed and modeled. Sources for the phase noise of the clock output at the resonance frequency are identified, including the power supply, the heatsink, and the external crystal. Low-frequency resonance is detected and validated to be caused by the external crystal grounding design. Solutions to decrease crystal-related noise are proposed and validated. In addition, the sensitivity based on the signal-to-noise ratio is proposed and verified with measurements to numerically analyze the effects of power supply noise on clock phase noise. The proposed phase noise sensitivity is extracted from the measured phase noise results and can be used to estimate the phase noise and jitter of different power supply noises. The extraction and prediction methods are validated with different buffer types, including low-voltage differential signal, high-speed current steering logic, low-voltage positive emitter-coupled logic, and low-voltage complementary metal–oxide–semiconductor, in a device under test with the given design.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"150-159"},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Radial Basis Function Network-Based Surrogate-Assisted Swarm Intelligence Approach for Fast Optimization of Power Delivery Networks 一种基于径向基函数网络的代理辅助群智能快速优化输电网络的方法

IEEE Transactions on Signal and Power Integrity Pub Date : 2022-10-25 DOI: 10.1109/TSIPI.2022.3217109

Heman Vaghasiya;Akash Jain;Jai Narayan Tripathi

{"title":"A Radial Basis Function Network-Based Surrogate-Assisted Swarm Intelligence Approach for Fast Optimization of Power Delivery Networks","authors":"Heman Vaghasiya;Akash Jain;Jai Narayan Tripathi","doi":"10.1109/TSIPI.2022.3217109","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3217109","url":null,"abstract":"The design and optimization of power delivery networks (PDNs) in very large scale integration systems are becoming very challenging with the increasing complexity of such systems. Decoupling capacitors are the key elements used in a PDN to minimize power supply noise and to maintain low impedance of the PDN to avoid system failure. In this article, a novel approach using surrogate-assisted swarm intelligence is presented for efficient and fast optimization of PDNs. For generating the surrogate models, a standard radial basis function network is used. Using the proposed approach, the decoupling capacitors are selected and placed optimally, eventually reducing the cumulative impedance of the PDN below the target impedance. The performance comparison between the conventional and the surrogate-assisted approach is presented. Three case studies are presented on a practical system to demonstrate the competence of the proposed approach. The results obtained by the proposed approach are also compared with the same obtained by the state-of-the-art approaches. For the proposed approach, the runtime is drastically reduced compared to the state-of-the-art approaches for the optimization problem without having any effect on the performance. The consistency of results in all of the case studies confirms the validity of the proposed approach.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"140-149"},"PeriodicalIF":0.0,"publicationDate":"2022-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

An Empirical Modeling of Far-End Crosstalk and Insertion Loss in Microstrip Lines 微带线中远端串扰和插入损耗的经验模型

IEEE Transactions on Signal and Power Integrity Pub Date : 2022-10-12 DOI: 10.1109/TSIPI.2022.3214172

Yuanzhuo Liu;Shaohui Yong;Yuandong Guo;Jiayi He;Chaofeng Li;Xiaoning Ye;Jun Fan;Victor Khilkevich;DongHyun Kim

{"title":"An Empirical Modeling of Far-End Crosstalk and Insertion Loss in Microstrip Lines","authors":"Yuanzhuo Liu;Shaohui Yong;Yuandong Guo;Jiayi He;Chaofeng Li;Xiaoning Ye;Jun Fan;Victor Khilkevich;DongHyun Kim","doi":"10.1109/TSIPI.2022.3214172","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3214172","url":null,"abstract":"The difference in the dielectric permittivity of the different dielectric layers (including air) surrounding the microstrip is one of the major contributors to the far-end crosstalk (FEXT) in microstrip lines. The dielectric of the microstrip in printed circuit boards (PCBs) fabrication usually consists of two layers: the solder mask layer and the substrate layer. The characterization of the relative permittivity (\u0000<inline-formula><tex-math>${boldsymbol{varepsilon }}_{boldsymbol{r}}$</tex-math></inline-formula>\u0000) and dielectric dissipation factor (tan\u0000<italic>δ</i>\u0000) for the dielectric layers of the microstrip are important parameters for board-level electronic system designs. In addition, the foil surface roughness cannot be ignored for the conductor loss modeling. In this work, an extraction method with high accuracy is proposed to characterize the dielectric material and foil surface roughness properties from the measured S-parameters with known cross-sectional geometry up to 20 GHz. With the extracted properties, the FEXT and insertion loss of the microstrip can be estimated more accurately, providing design guidelines for PCB design and the material selection of the microstrip.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"130-139"},"PeriodicalIF":0.0,"publicationDate":"2022-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Analysis of Power-via-Induced Quasi-Quarter-Wavelength Resonance to Reduce Crosstalk 通过感应准四分之一波长谐振降低串扰的功率分析

IEEE Transactions on Signal and Power Integrity Pub Date : 2022-09-28 DOI: 10.1109/TSIPI.2022.3209138

Siqi Bai;Yuanzhuo Liu;Jongjoo Lee;Bichen Chen;Srinivas Venkataraman;Xu Wang;Bo Pu;Jun Fan;DongHyun Kim

{"title":"Analysis of Power-via-Induced Quasi-Quarter-Wavelength Resonance to Reduce Crosstalk","authors":"Siqi Bai;Yuanzhuo Liu;Jongjoo Lee;Bichen Chen;Srinivas Venkataraman;Xu Wang;Bo Pu;Jun Fan;DongHyun Kim","doi":"10.1109/TSIPI.2022.3209138","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3209138","url":null,"abstract":"Currently, power pins are increasingly used in package design to serve a dual purpose: to support crosstalk isolation between high-speed signals and to provide power delivery to serializer/deserializer input/output. This approach can reduce the overall pin count and subsequently limit the package body size to remain within a ball grid array form factor. However, for printed circuit boards (PCBs) in which power vias are adjacent to signal vias, increased far-end crosstalk (FEXT) and resonance in insertion loss can be observed, due to the quasi-quarter-wavelength resonance of the power via stub. Using an analytical model and 3-D full-wave simulation models, a physical explanation for this unexpected resonance in differential signal pairs is proposed. Considering the difficulty in changing the pin map of the IC package, several PCB layouts are proposed to eliminate the power-via-induced quasi-quarter-wavelength resonance without the need to change the package pin map. Upon application of the proposed methods, the resonance is eliminated, and the FEXT is reduced.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"121-129"},"PeriodicalIF":0.0,"publicationDate":"2022-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Far-End Crosstalk Modeling and Prediction for Stripline With Inhomogeneous Dielectric Layers (IDLs) 非均匀介质层带状线的远端串扰建模与预测

IEEE Transactions on Signal and Power Integrity Pub Date : 2022-08-31 DOI: 10.1109/TSIPI.2022.3203031

Yuanzhuo Liu;Shaohui Yong;Yuandong Guo;Jiayi He;Chaofeng Li;Xiaoning Ye;Jun Fan;DongHyun Kim

{"title":"Far-End Crosstalk Modeling and Prediction for Stripline With Inhomogeneous Dielectric Layers (IDLs)","authors":"Yuanzhuo Liu;Shaohui Yong;Yuandong Guo;Jiayi He;Chaofeng Li;Xiaoning Ye;Jun Fan;DongHyun Kim","doi":"10.1109/TSIPI.2022.3203031","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3203031","url":null,"abstract":"Far-end crosstalk (FEXT) is a critical factor that limits signal integrity performance in high-speed systems. The FEXT level is sensitive to the dielectric inhomogeneity of the stripline in fabricated printed circuit boards (PCBs). The dielectric of the stripline is manufactured with multiple inhomogeneous dielectric layers (IDLs) of various resin and glass fiber bundles. A marginal difference in the dielectric permittivity of the IDLs can lead to a significant change FEXT level. In this article, a practical FEXT modeling methodology for striplines is proposed by introducing the extraction method for \u0000<inline-formula><tex-math>${{boldsymbol{varepsilon }}}_{boldsymbol{r}}$</tex-math></inline-formula>\u0000 of IDLs. The new stripline model is constructed with three IDLs comprised of core, prepreg, and resin pocket, to improve the model accuracy. With the cross-sectional geometry and measured S-parameters of the coupled striplines, \u0000<inline-formula><tex-math>${{boldsymbol{varepsilon }}}_{boldsymbol{r}}$</tex-math></inline-formula>\u0000 of IDLs can be extracted. In addition, an analytical model to predict the FEXT polarity and magnitude of the stripline caused by the inhomogeneity is proposed targeted for prelayout application. The proposed models have been verified using measurement. The proposed models can provide useful analysis methodology and design guidelines to mitigate the FEXT level in high-speed systems, especially for high-volume PCB tests in the prelayout and postlayout stages.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"93-103"},"PeriodicalIF":0.0,"publicationDate":"2022-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Automated Framework for Variability Analysis for Integrated Circuits Using Metaheuristics 集成电路变率分析的元启发式自动化框架

IEEE Transactions on Signal and Power Integrity Pub Date : 2022-08-29 DOI: 10.1109/TSIPI.2022.3202150

Aksh Chordia;Jai Narayan Tripathi

引用次数: 2

Signal Integrity Assessment of Interconnects Routed Within Bandgap Metallic Cavities 带隙金属空腔内布线互连的信号完整性评估

IEEE Transactions on Signal and Power Integrity Pub Date : 2022-08-17 DOI: 10.1109/TSIPI.2022.3199331

Francesco de Paulis;Muhammet Hilmi Nisanci

引用次数: 0

Extraction of Single Cell Impedance From Battery Module Measurement by Simulation-Based De-Embedding 基于仿真的去嵌入从电池模块测量中提取单电池阻抗

IEEE Transactions on Signal and Power Integrity Pub Date : 2022-08-17 DOI: 10.1109/TSIPI.2022.3199178

Herbert Hackl;David J. Pommerenke;Martin Ibel;Bernhard Auinger

引用次数: 1