非均匀介质层带状线的远端串扰建模与预测

Yuanzhuo Liu;Shaohui Yong;Yuandong Guo;Jiayi He;Chaofeng Li;Xiaoning Ye;Jun Fan;DongHyun Kim
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引用次数: 0

摘要

在高速系统中,远端串扰(FEXT)是限制信号完整性性能的关键因素。FEXT水平对制造的印刷电路板(PCB)中带状线的介电不均匀性敏感。带状线的电介质由各种树脂和玻璃纤维束的多个不均匀电介质层(IDL)制成。IDL的介电常数的边际差异可以导致FEXT水平的显著变化。在本文中,通过介绍IDL的${\boldsymbol{\varepsilon}}_{\boltsymbol{r}}$的提取方法,提出了一种实用的带状线FEXT建模方法。新的带状线模型由芯、预浸料和树脂袋三个IDL组成,以提高模型的精度。利用耦合带状线的横截面几何形状和测量的S参数,可以提取IDL的${\boldsymbol{\varepsilon}}_{\bold symbol{r}}$。此外,针对预布局应用,提出了一个分析模型来预测由不均匀性引起的带线的FEXT极性和幅度。所提出的模型已经通过测量进行了验证。所提出的模型可以提供有用的分析方法和设计指南,以降低高速系统中的FEXT水平,特别是对于布局前和布局后阶段的高容量PCB测试。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Far-End Crosstalk Modeling and Prediction for Stripline With Inhomogeneous Dielectric Layers (IDLs)
Far-end crosstalk (FEXT) is a critical factor that limits signal integrity performance in high-speed systems. The FEXT level is sensitive to the dielectric inhomogeneity of the stripline in fabricated printed circuit boards (PCBs). The dielectric of the stripline is manufactured with multiple inhomogeneous dielectric layers (IDLs) of various resin and glass fiber bundles. A marginal difference in the dielectric permittivity of the IDLs can lead to a significant change FEXT level. In this article, a practical FEXT modeling methodology for striplines is proposed by introducing the extraction method for ${{\boldsymbol{\varepsilon }}}_{\boldsymbol{r}}$ of IDLs. The new stripline model is constructed with three IDLs comprised of core, prepreg, and resin pocket, to improve the model accuracy. With the cross-sectional geometry and measured S-parameters of the coupled striplines, ${{\boldsymbol{\varepsilon }}}_{\boldsymbol{r}}$ of IDLs can be extracted. In addition, an analytical model to predict the FEXT polarity and magnitude of the stripline caused by the inhomogeneity is proposed targeted for prelayout application. The proposed models have been verified using measurement. The proposed models can provide useful analysis methodology and design guidelines to mitigate the FEXT level in high-speed systems, especially for high-volume PCB tests in the prelayout and postlayout stages.
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