IEEE Transactions on Signal and Power Integrity最新文献

{"title":"Power Supply Induced Jitter: Introduction and Recent Advances","authors":"Chulsoon Hwang;Jai Narayan Tripathi;Dan Oh","doi":"10.1109/TSIPI.2026.3665467","DOIUrl":"https://doi.org/10.1109/TSIPI.2026.3665467","url":null,"abstract":"Jitter is a critical concern in modern electronic systems, particularly as semiconductor devices increasingly operate with low supply rails to minimize power consumption. This article provides a comprehensive review of power supply induced jitter (PSIJ), which refers to timing variations directly caused by fluctuations in the power supply voltage. It examines the fundamental mechanisms of PSIJ and presents generalized models for predicting jitter. System-level jitter tracking characteristics are analyzed for serial links, memory interfaces, and synchronous logic to explain the resulting jitter spectrum. The article also summarizes various presilicon PSIJ modeling techniques, including time-domain, frequency-domain, slope-based, and delay-based methods. Finally, recent advancements in PSIJ research are discussed.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"22-32"},"PeriodicalIF":0.0,"publicationDate":"2026-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147362555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Surrogate Model-Assisted Optimization for Ultrawideband Bidirectional Absorptive Common-Mode Filter Design","authors":"Yuan He;Gongda Hu;Gang Wang;Qingfu Zhang","doi":"10.1109/TSIPI.2026.3665470","DOIUrl":"https://doi.org/10.1109/TSIPI.2026.3665470","url":null,"abstract":"An efficient surrogate model-assisted optimization scheme for designing ultrawideband bidirectional absorptive common-mode filters (A-CMFs) is presented. The proposed A-CMF consists of a differential pair, two resistors, and a lossless network constructed by fragment-type defected ground structure (FTDGS). Excellent differential mode (DM) transmission and common mode (CM) absorption characteristics are achieved by optimizing the lossless network and resistors. The computationally efficient initial optimization uses coarse FTDGS grids and aims at obtaining the good candidate solution set to establish a low-cost surrogate model. Guided by the surrogate model, the subsequent optimization uses the improved initial values, which involves adjusting structure configuration and conducting effective structure initialization to improve circuit performance and optimization efficiency thus achieving an A-CMF with enhanced DM passband and CM absorption bandwidth. For demonstration, an ultrawideband bidirectional A-CMF is designed on a printed circuit board with a design area of 0.0512 λ_g². Measurement results show that the A-CMF has a DM 3-dB cutoff frequency up to 11.7 GHz and a CM absorption band from 1.92 to 11.05 GHz (the fractional bandwidth is 140.8%), covering all communication bands of the public standard IEEE 802.11be.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"33-42"},"PeriodicalIF":0.0,"publicationDate":"2026-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147440685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast Estimation of Frequency Response for Full-Channel via-Trace Structures up to 60 GHz","authors":"Davit Kharshiladze;Yifan Ding;Hyunwook Park;Mehdi Mousavi;Natalia Bondarenko;Hanqin Ye;Francis Smith;Brice Achkir;Chulsoon Hwang","doi":"10.1109/TSIPI.2026.3652937","DOIUrl":"https://doi.org/10.1109/TSIPI.2026.3652937","url":null,"abstract":"Physics-based via models are used in combination with neural network (NN) prediction of stripline to accurately estimate the full-channel response of trace-via structures for multilayered boards. Vias are modeled using analytical expressions for via capacitance and parallel plate impedance. Stripline response is predicted using a pretrained NN and converted into a circuit representation utilizing modal decomposition. The via-stripline transition is modeled with lumped elements. Individual elements are then concatenated using a segmentation approach. It is shown that such an approach can estimate frequency response up to 60 GHz. Correlation with full-wave solvers is demonstrated, and substantially improved computational speed is presented.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"10-21"},"PeriodicalIF":0.0,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2025 Index IEEE Transactions on Signal and Power Integrity","authors":"","doi":"10.1109/TSIPI.2026.3652338","DOIUrl":"https://doi.org/10.1109/TSIPI.2026.3652338","url":null,"abstract":"","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2026-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11345459","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Electromagnetic Compatibility Society Information","authors":"","doi":"10.1109/TSIPI.2025.3650011","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3650011","url":null,"abstract":"","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2026-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11329428","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"PDN Impedance Qualification With the Uncertainties From Decoupling Capacitor Specifications","authors":"Shruti Sawant;Faye Squires;Sam Connor;Matthew Doyle;Matteo Cocchini;Dylan Grace;Francesco De Paulis;Lijun Jiang","doi":"10.1109/TSIPI.2026.3711396","DOIUrl":"https://doi.org/10.1109/TSIPI.2026.3711396","url":null,"abstract":"Decoupling capacitors are essential components for power integrity optimization of the power distribution networks (PDNs). In practical designs, capacitors and their parasitic inductance have statistical deviations from nominal values, due to fabrication tolerances, temperature, aging and applied DC and AC voltage levels. This work presents a framework to evaluate the impact of such uncertainties on <inline-formula><tex-math>$Z_{text{input}}$</tex-math></inline-formula>, the input impedance of the PDN at the evaluation port (normally at the die side of the system). Closed-form expressions are derived for the mean and variance of the input impedance, <inline-formula><tex-math>$Z_{text{input}}$</tex-math></inline-formula>, by modeling capacitance (<italic>C</i>) and equivalent series inductance as random variables. The framework explicitly captures parameter sensitivities, showing that equivalent series resistance (ESR) plays a critical role for the sensitivity control. The results demonstrate that increasing ESR suppresses resonance peaks and reduces the variance, suggesting that optimal ESR values can stabilize the PDN without excessively raising baseline impedance. Furthermore, analysis of multiport PDNs shows that variance decreases rapidly with the first few decaps and then saturates, consistent with the law of large numbers, thereby identifying a practical tradeoff point for decap count. A mathematical proof is presented to show that the variance decreases versus 1/<inline-formula><tex-math>$N_{text{eff}}$</tex-math></inline-formula>, where <inline-formula><tex-math>$N_{text{eff}}$</tex-math></inline-formula> is the effective number of decaps. Finally, the method is extended to non-Gaussian parameter distributions (lognormal, gamma, and beta), showing that the conclusions remain valid beyond Gaussian assumptions. Overall, the proposed approach provides a computationally efficient and robust tool for statistical PDN analysis and offers design guidelines for the decap selection, ESR tuning under variations in decap properties.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"132-140"},"PeriodicalIF":0.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148748309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of Power/Ground Microvia Placement in Multiple Power Domain 3D-IC Package Substrates Using Deep Reinforcement Learning","authors":"Seunghun Ryu;Seonghi Lee;Sanguk Lee;Hyunwoo Kim;Seongho Woo;Dongryul Park;Jinwook Lee;Dongkyun Kim;Seokbeom Yong;Sangsub Song;Seungyoung Ahn","doi":"10.1109/TSIPI.2026.3714430","DOIUrl":"https://doi.org/10.1109/TSIPI.2026.3714430","url":null,"abstract":"This article proposes a deep reinforcement learning (DRL) approach for optimizing the placement of power/ground microvias within the package substrate of 3D-ICs in multiple power domain (MPD) environments. The package substrate facilitates power and ground delivery to the appropriate power domains and components; however, its design for power integrity presents significant complexity due to three-dimensional interconnections and varying power densities. The complicated interactions between MPD components and current profiles obscure the analysis of the power noise, necessitating an advanced optimization methodology. To address this challenge, a DRL-based microvia placement optimization method considering MPD is introduced. The encoder, implemented using a convolutional neural network, captures high-level features from the package power/ground planes and simultaneous switching current spectrum, while the decoder, employing a gated recurrent unit-based network, sequentially determines microvia positions. Furthermore, the proposed method demonstrates generalization by being trained on random current profiles and arbitrary plane layouts. Comparative evaluations against conventional optimization algorithms, including random search and genetic algorithms, confirm the superiority of the proposed method in terms of both the execution time and solution optimality.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"154-170"},"PeriodicalIF":0.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148748958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Physics-Assisted Genetic Algorithm for Efficient Co-optimization of PDN Pinmap and Decoupling Capacitors","authors":"Bolin Meng;Li Jiang;Liang Zhao;Er-Ping Li;Ling Zhang","doi":"10.1109/TSIPI.2026.3732255","DOIUrl":"https://doi.org/10.1109/TSIPI.2026.3732255","url":null,"abstract":"This article proposes a physics-assisted genetic algorithm (PAGA) for efficient co-optimization of pinmap and decoupling capacitors (decaps) in power distribution networks (PDNs). In many existing PDN design workflows, pinmap optimization and decap design are often treated as largely independent tasks: Decap optimization is primarily used to suppress impedance peaks, while pinmap design of integrated circuits (ICs) is typically optimized in isolation. Such a decoupled strategy may lead to suboptimal solutions and increased design cost. This work proposes a two-stage serial co-optimization framework that systematically integrates pinmap and decap design. First, a PAGA with a neighborhood condensation operator is proposed to minimize the bare PDN parasitic inductance by leveraging geometric electromagnetic heuristics to efficiently reposition suboptimal pins. The second stage then performs optimal decap selection and placement on the improved low-inductance pinmap. Experimental results show that the proposed PAGA improves convergence efficiency by over 50% compared to a conventional genetic algorithm, and the overall framework achieves superior power integrity performance with significantly fewer capacitors than decap-only optimization approaches, offering a computationally efficient path toward low-cost and high-performance PDN design.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"217-225"},"PeriodicalIF":0.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149131766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advanced Spike Signal Equalization via Long Short-Term Memory Neural Network","authors":"Quankun Chen;Ling Zhang;Yining Jiang;Da Li;Wenchao Chen;Hanzhi Ma;Er-Ping Li","doi":"10.1109/TSIPI.2026.3686803","DOIUrl":"https://doi.org/10.1109/TSIPI.2026.3686803","url":null,"abstract":"Spike neural networks and neuromorphic chips and chiplets have recently drawn increasing attention. However, these systems utilize spike signals and address-event representation protocols, which differ fundamentally from traditional digital circuits. As a result, they may face different signal integrity issues and require special equalization methods. This article presents a long short-term memory (LSTM) based signal equalization approach that effectively addresses spike signal equalization of different data rates. This LSTM equalization method exhibits outstanding scalability in restoring spike signals at different data rates using one trained model. By implementing the LSTM equalization approach, high-precision signal equalization for spike signals is achieved, which demonstrates a remarkable advantage over conventional feed-forward equalization. These results verify the effectiveness of the proposed method for high-precision spike signal equalization and highlight its potential for neuromorphic and spike-based interconnect systems.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"71-80"},"PeriodicalIF":0.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147828962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reinforcement Learning for Decoupling Capacitor Optimization in Postlayout PDNs Using Transformer Architecture","authors":"Haran Manoharan;Hanfeng Wang;Chulsoon Hwang","doi":"10.1109/TSIPI.2026.3691276","DOIUrl":"https://doi.org/10.1109/TSIPI.2026.3691276","url":null,"abstract":"In this article, a novel transformer-based reinforcement learning framework is proposed for postlayout power distribution network (PDN) decoupling capacitor (decap) optimization. The model is designed to be scalable and generalizable to any number of impedance observation ports, decap placement ports, and candidate capacitors. The proposed approach uses a sequential transformer decoder that learns to assign capacitors port-by-port, guided by impedance deviation and port priority features derived from the PDN's frequency-dependent impedance response. At each step, the model embeds the current system state, including the delta between observed and target impedance, and uses attention to select the most suitable decap from a candidate library. The model is trained via reinforcement learning, where the policy is optimized to minimize impedance violations and reduce capacitor usage. The architecture supports rapid adaptation to new decap libraries. Compared to traditional optimization techniques such as genetic algorithms, which may require hours, the proposed model produces high-quality results in seconds, while maintaining adaptability across varying PDN configurations. The results demonstrate the model's robustness in handling real-world PDN scenarios with diverse port and component configurations.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"81-92"},"PeriodicalIF":0.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148003646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}