IEEE Transactions on Signal and Power Integrity最新文献

{"title":"An Efficient Fixture Removal Embedded Modeling Method Based on TDR and CNN Technique","authors":"Si-Yao Tang;Xing-Chang Wei;Richard Xian-Ke Gao","doi":"10.1109/TSIPI.2025.3560949","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3560949","url":null,"abstract":"<italic>S</i>-parameters are typically employed in equivalent circuit (EC) modeling of electronic devices. However, for existing modeling procedures, the impact of fixtures on <italic>S</i>-parameter measurement cannot be neglected and needs to be eliminated through de-embedding before modeling. This letter proposes a new approach that integrates fixture removal into the modeling procedure by combining time-domain reflection and convolutional neural network techniques. The proposed approach bypasses the need for separate de-embedding, allowing for direct derivation of the EC model. Different to the traditional modeling procedure, its advantages in simplifying the modeling procedure and avoiding the errors introduced by de-embedding have been validated by the physical measurement.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"132-135"},"PeriodicalIF":0.0,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143883335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reinforcement-Learning-Based Optimization of Bonding Wires for EMI Mitigation","authors":"Wenchang Huang;Muqi Ouyang;Yin Sun;Jongjoo Lee;Chulsoon Hwang","doi":"10.1109/TSIPI.2025.3560229","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3560229","url":null,"abstract":"Wire bonding as a metallic interconnection is widely used to transmit high-speed signals and supply power within the integrated circuit (IC) packages. However, bonding wires also effectively radiate power noise and the harmonics of the output signals, causing electromagnetic interference and radio frequency interference issues. In this study, a current-loop model using a transfer admittance matrix for estimating the equivalent radiation sources of an IC/package featuring bonding wires is proposed. Based on the proposed modeling method, a novel reinforcement learning algorithm is applied to optimize the configurations of signal, power, and ground bonding wires, mitigating the radiation from the IC/package. The proposed modeling method is validated experimentally by a self-designed IC with an inverter-type buffer based on a complementary metal–oxide–semiconductor 0.18-μm process, and a radio frequency victim antenna built on the same printed circuit board. From 720 to 900 MHz, the maximum difference between the proposed modeling method and the measurement results is only 2.3 dB. In addition, full-wave simulation is performed to evaluate the optimization results of the reinforcement learning algorithm, showing radiation mitigation of over 7 dB compared to the randomly selected bonding-wire configurations.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"124-131"},"PeriodicalIF":0.0,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143883336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mode-Dependent Effective Dielectric Constants of Inhomogeneous Dielectric Layers for PCB Applications","authors":"Chaofeng Li;Mehdi Mousavi;Seyed Mostafa Mousavi;Reza Asadi;Xiaoning Ye;DongHyun Kim","doi":"10.1109/TSIPI.2025.3558202","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3558202","url":null,"abstract":"The dielectric substrate of printed circuit boards (PCBs) generally consists of epoxy or polyurethane resin and fiberglass, which can be modeled as inhomogeneous dielectric layers (IDLs). IDLs are not homogeneous in the perpendicular direction of the layers’ interface, which means that they constitute an anisotropic material. Thus, the effective dielectric constant (Dk) for IDLs is direction dependent, i.e., mode dependent. In this study, the effective Dk values of IDLs are extracted for different modes using three commonly used full-wave simulation models: the transverse electric (TE), transverse magnetic (TM), and equivalent parallel-plate capacitor models. The results for the TE and TM modes showed a 10% discrepancy. The effective Dk of IDLs was efficiently estimated by the parallel-plate capacitor model based on the layers’ dielectric properties and thicknesses. Moreover, the analytical formulas of resonance frequency for a cylindrical cavity resonator filled with IDLs were derived to extract the effective Dk of the IDLs at different resonance modes, which could be used as a guideline of resonator methods for PCB material characterization. These results correlated with the results from the equivalent parallel capacitor model. Finally, the impact of IDL anisotropy on transmission line loss and time-domain reflectometry impedance was analyzed based on full-wave simulation.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"116-123"},"PeriodicalIF":0.0,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143875274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Generalized Mixed-Mode S-Parameter Framework for Accurate Multipair Crosstalk Analysis in High-Speed Digital Channels","authors":"Manish K. Mathew;Xiao-Ding Cai;Chaofeng Li;Mehdi Mousavi;Reza Asadi;Junyong Park;Shameem Ahmed;Bidyut Sen;DongHyun Kim","doi":"10.1109/TSIPI.2025.3557786","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3557786","url":null,"abstract":"The accuracy of mixed-mode S-parameter conversion is important for crosstalk mitigation in high-speed digital systems. However, the conventional mixed-mode S-parameter formulation assumes equal even-mode and odd-mode impedances<inline-formula><tex-math>$ ( { {{{{Z}}}_{{{oo}}}} = {{{{Z}}}_{{{oe}}}} } )$</tex-math></inline-formula>, which limits its applicability, particularly in tightly coupled differential structures. In this article, we propose a novel mixed-mode S-parameter generalization (generalized M1/M2 approach) using an N-differential port network, which allows for multipair (i.e., pair-to-pair) crosstalk analysis on coupled differential systems, given by:<inline-formula><tex-math>$ {{[ {{{{{S}}}_{{{mm}}}}} ]}_{{{i}} times {{i}}}} = ({{[ {{{{{M}}}_1}} ]}_{{{i}} times {{i}}}} times {{[ {{{{{S}}}_{{s}}}} ]}_{{{i}} times {{i}}}} + {{[ {{{{{M}}}_2}} ]}_{{{i}} times {{i}}}}) times {{( {{{{[ {{{{{M}}}_1}} ]}}_{{{i}} times {{i}}}} + {{{[ {{{{{M}}}_2}} ]}}_{{{i}} times {{i}}}} times [ {{{{{S}}}_{{s}}}} ]} )}^{ - 1}}$</tex-math></inline-formula>. The proposed M1/M2 formulation eliminates the need for renormalization by integrating mode-dependent coupling factors <inline-formula><tex-math>${{{{k}}}_{{{oo}}}} {and} {{{{k}}}_{{{oe}}}},$</tex-math></inline-formula> ensuring a more physically meaningful representation of mixed-mode S-parameters, thereby improving the accuracy of both intrapair and interpair crosstalk analysis in high-speed digital systems. The effectiveness of the proposed M1/M2 approach is demonstrated through intrapair and interpair analysis on tightly coupled striplines, revealing peak-to-peak variations in differential return loss, interpair near-end crosstalk, and far-end crosstalk. Validation using a differential setup with commercial tools (Balun approach) confirmed the formulation's accuracy, with errors below 1%. In addition, measurement validation on a microstrip differential pair highlighted the model's scalability and precision, emphasizing the importance of incorporating mode-dependent impedance variations.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"96-108"},"PeriodicalIF":0.0,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143856146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimizing Equalizations of FFE, CTLE, and DFE Jointly Through a Single Pulse Response","authors":"Yen-Hao Chen;Chun-I Tseng;Ding-Bing Lin","doi":"10.1109/TSIPI.2025.3557370","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3557370","url":null,"abstract":"With the increasing data rate of high-speed digital systems, equalization techniques have been widely applied to counteract intersymbol interference and maximize eye opening in today's high-speed serial links. Channel simulations with optimal equalization settings allow engineers to explore design tradeoffs, reduce the need for costly prototypes, and ensure robust performance before manufacturing. Existing equalization optimization methods require either iterative interaction with commercial channel simulators during the optimization process, developing models with extensive training data before optimization, or separately optimizing linear equalizers in the frequency domain. In this article, the method to jointly optimize feedforward equalization, continuous-time linear equalization, and decision feedback equalization at the transmitter, receiver, or both is proposed. The optimization is achieved through the analysis of a nonequalized pulse response, eliminating the computational cost of channel simulations during optimization. Practical examples using non-return-to-zero (NRZ) and pulse amplitude modulation four-level (PAM4) signaling schemes demonstrate the effectiveness of the proposed method. A comparison with the Bayesian optimization approach, a widely discussed method for equalization optimization, shows that while both methods achieve nearly identical optimal eye openings, the proposed method offers significantly higher optimization efficiency.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"88-95"},"PeriodicalIF":0.0,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143840091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Verification of Wired Channels Beyond 100 Gbps","authors":"Francesco de Paulis;Richard Mellitz;Luis Boluna;Mike Resso;Rick Rabinovich","doi":"10.1109/TSIPI.2025.3557371","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3557371","url":null,"abstract":"The increase of the data rate beyond 100 Gbps for wired channels, such as the Chip-to-Module interfaces, requires a very careful evaluation and optimization of the transmitter and receiver properties and equalization capabilities based on the specific passive channel of interest. The channel operating margin (COM) methodology offered in the IEEE Standard for Ethernet 802.3 is developed for such purpose. It is adopted in this article to demonstrate how it can be used while paving a rigorous step-by-step procedure for the transmitter characterization and the reliable evaluation of the receiver equalization. A wide range of experiments are carried out to demonstrate the effective applicability of the COM method for optimizing the 100 Gbps four-level pulse amplitude modulation signaling and for pushing the channel design toward the length (and loss) limits.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"109-115"},"PeriodicalIF":0.0,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143856266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IBIS Model Simulation Accuracy Improvement by Including Nonlinear Power Supply Induced Jitter Effect","authors":"Yifan Ding;Randy Wolff;Zhiping Yang;Chulsoon Hwang","doi":"10.1109/TSIPI.2025.3551671","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3551671","url":null,"abstract":"The input/output buffer information specification (IBIS) model is limited in its ability to handle power supply induced jitter. In this article, a direct IBIS switching coefficient modification algorithm that improves IBIS simulation accuracy by including the nonlinear jitter effect is presented. Compared with the previous IBIS-modification algorithms, the new algorithm is more straightforward, as it considers the time-averaged power supply noise effect on both the switching coefficient transition edge and the output transition edge. By addressing the nonlinear jitter, the model is more robust under conditions of significant power supply noise, both in terms of the output waveform shape and jitter estimation. This modification algorithm is implemented on an inverter chain circuit and a realistic double data rate (DDR) model. The performance with dc power noise, ac power noise, and multitone power noise is validated. The new proposed algorithm significantly enhances jitter modeling accuracy, reducing the maximum jitter prediction error from 47.3% to 8.19% in the inverter chain case under complex multitone power noise and from a maximum of 80% to below 20% in the realistic DDR model, compared with the previous algorithm.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"55-64"},"PeriodicalIF":0.0,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143748737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comprehensive Measurement and Cross-Sectional Study of Decoupling Capacitor Interconnect Inductance","authors":"Yifan Ding;Faye Squires;Suho Lee;Albert E. Ruehli;Chulsoon Hwang","doi":"10.1109/TSIPI.2025.3550894","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3550894","url":null,"abstract":"The inductance associated with a decoupling capacitor (decap) is represented by its equivalent series inductance (ESL). However, the supplier specified ESL model pertains to a specific physical mounting situation. When mounted on printed circuit board, the datasheet ESL values do not accurately reflect the actual inductance, because of the mounting method and coupling with nearby structures, including connections to return planes through traces and vias. This inductance, <inline-formula><tex-math>${{bm{L}}_{mathbf{above}}}$</tex-math></inline-formula>, is influenced by the decap's connection pattern. Although larger package capacitors are generally assumed to lead to higher loop inductance, our measurements indicated that larger capacitors do not necessarily result in higher <inline-formula><tex-math>${{bm{L}}_{mathbf{above}}}$</tex-math></inline-formula>. The inner geometry of the capacitor and mounting structure was found to significantly influence <inline-formula><tex-math>${{bm{L}}_{mathbf{above}}}$</tex-math></inline-formula>. This study examined the effects of inner geometry on decap inductance, validated through extensive simulations and measurements. <inline-formula><tex-math>${{bm{L}}_{mathbf{above}}}$</tex-math></inline-formula> measurements for 31 types of decaps across four package sizes (0402 to 1206), with six samples tested per capacitor type, revealed overlapping inductance across sizes. Cross-sectional measurements indicated the exact electrode geometry. The determined geometry showed strong correlations between simulated and measured <inline-formula><tex-math>${{bm{L}}_{mathbf{above}}}$</tex-math></inline-formula> results, thus supporting the investigation of the effects of inner geometry on inductance. The relationship between <inline-formula><tex-math>${{bm{L}}_{mathbf{above}}}$</tex-math></inline-formula> and placement orientation was additionally examined.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"46-54"},"PeriodicalIF":0.0,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143748840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Hybrid Deep-Belief and Knowledge-Based Neural Network for Efficient Prediction of Jitter in the Presence of Multiple PDN Noise Sources","authors":"Ahsan Javaid;Ramachandra Achar;Jai Narayan Tripathi","doi":"10.1109/TSIPI.2025.3550155","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3550155","url":null,"abstract":"In this article, an efficient approach is developed to predict the jitter in the presence of multiple noise sources, such as power supply noise, ground bounce noise as well as input data noise in diverse power delivery modules by combining the knowledge-based neural network with the deep belief neural network. The proposed hybrid neural network achieves reasonable accuracy while providing for efficient training using input data obtained from both analytical closed-form expressions as well as a circuit simulator. The proposed model can also handle varying inputs without retraining the network's parameters. In order to optimize the training dataset, instead of using the random dataset, a new configuration with a mixed dataset (with a combination of uniformly distributed data as well as randomly distributed data) is proposed. Their performance along with different types of energy models is also investigated.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"33-45"},"PeriodicalIF":0.0,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143748841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fine-Grained Modeling and Evaluation of 3-D Power Distribution Networks in Logic-on-Memory Stacking Architecture","authors":"Ang Li;Pengyu Liu;Zizheng Dong;Jinhao Li;Jianfei Jiang;Weijia Zhu;Naifeng Jing;Qin Wang","doi":"10.1109/TSIPI.2025.3548965","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3548965","url":null,"abstract":"With the escalating computing power demands in artificial intelligence-generated content and other applications, the three-dimensional (3-D) stacking technology has effectively broken through the bottleneck of Moore's law and become the primary choice for high-performance chip packaging technology. Especially in the logic-on-memory (LoM) scenario with strong industrial feasibility, the 3-D stacking process fully leverages its advantages of extremely high interconnection density and low communication delay, making it well-suited for addressing the bandwidth expansion challenges under the “memory wall” bottleneck. Nevertheless, the heightened integration level and reduced power consumption requirements of the LoM architecture have introduced significant challenges to the power supply of stacking chips. Current EDA tools lack the capability to rapidly and effectively explore the optimal design of LoM power distribution networks (PDNs), and existing SPICE-type 3-D PDN analysis models often encounter challenges with oversimplified modeling approach and idealized power analysis, rendering them unsuitable for LoM structures, such as near-memory computing and high-bandwidth processors in computing/memory stacking scenarios. In this work, we propose for the first time a fine-grained 3-D PDN analysis modeling approach designed for LoM stacking architecture. Our modeling method comprehensively accounts for the power supply characteristics within the stacking architectures, and implements fine-grained segmentation and modeling of the full-chip PDN based on the estimated area, power consumption, and backend-of-line dimensions, allowing for rapid and accurate evaluation of power integrity (PI) across different PDN design schemes before the physical design stage. Furthermore, we explore the optimal 3-D LoM PDN design across various physical design spaces, including multilayer PDN connection schemes, metal layer configuration, and through-silicon via placement density. The final analysis result is applied to guide the practical physical design of the LoM PDN, highlighting the significance of our modeling approach in 3-D chip PI analysis and 3-D PDN design optimization.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"65-80"},"PeriodicalIF":0.0,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143792932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}