IEEE Transactions on Signal and Power Integrity最新文献_第2页

Effective High-Speed via Model Considering Equivalent High-Order-Mode Inductance 考虑等效高阶模式电感的有效高速通路模型

IEEE Transactions on Signal and Power Integrity Pub Date : 2024-10-29 DOI: 10.1109/TSIPI.2024.3487539

Chaofeng Li;Xiao-Ding Cai;Manish K. Mathew;Junyong Park;Mehdi Mousavi;Shameem Ahmed;Bidyut Sen;DongHyun Kim

{"title":"Effective High-Speed via Model Considering Equivalent High-Order-Mode Inductance","authors":"Chaofeng Li;Xiao-Ding Cai;Manish K. Mathew;Junyong Park;Mehdi Mousavi;Shameem Ahmed;Bidyut Sen;DongHyun Kim","doi":"10.1109/TSIPI.2024.3487539","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3487539","url":null,"abstract":"A high-speed via model considering equivalent high-order-mode inductance for frequencies above 70 GHz is proposed in this article. The proposed via model, which considers the equivalent high-order-mode inductance, is a high-accuracy and high-bandwidth via model, improved from the previously proposed mode-decomposition-based equivalent via (MEV) model. The equivalent high-order-mode inductance is an inductance produced by the magnetic fields of high-order modes in the via domain. By including the empirical equivalent high-order-mode inductance, the proposed via model accurately predicts the insertion and return losses of the via with a large antipad size up to the frequency of 150 GHz, which expands the application range of the previously proposed MEV model. In this article, the limitation of the previously proposed MEV model is analyzed by comparing the input impedance extracted from the MEV model and the full-wave simulation. An empirical closed-form formula is proposed to calculate the equivalent high-order-mode inductance at high frequencies to improve the accuracy of the previously proposed model. In addition, the proposed single high-speed via model was expanded to a differential via pair model. The proposed high-speed via model was verified using simulation and measurement results.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"169-177"},"PeriodicalIF":0.0,"publicationDate":"2024-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142671987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimized Signal and Power Integrity of Silicon Interposer for HBM2E in CoWoS Packaging 针对 CoWoS 封装中的 HBM2E 优化硅集成电路的信号和功率完整性

IEEE Transactions on Signal and Power Integrity Pub Date : 2024-10-29 DOI: 10.1109/TSIPI.2024.3487547

Kuei-Ju Lin;Chien-Min Lin;Ruey-Beei Wu

{"title":"Optimized Signal and Power Integrity of Silicon Interposer for HBM2E in CoWoS Packaging","authors":"Kuei-Ju Lin;Chien-Min Lin;Ruey-Beei Wu","doi":"10.1109/TSIPI.2024.3487547","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3487547","url":null,"abstract":"As high-speed digital systems require faster transmission and computing speed, the impact of complex interconnects in a limited space on the electrical performance of the channel-link system becomes more and more serious. This article aims to optimize the interconnection links between the enhanced second-generation high-bandwidth memory modules and systems on chip (CPU or GPU) for achieving the optimized signal and power integrity. Since the signal lines are susceptible to crosstalk, an improved diagonal-staggering wiring scheme is proposed to reduce the coupling coefficient between the signal lines by at least five times. The contour map for the mismatched systems with the peak distortion analysis is then applied to quickly find the optimal impedance design of lines for the best eye diagram. At a data rate of 6.4 Gb/s with a rise time of 15 ps, the eye height is optimized to be 4.6 times that in the original layout. Finally, the power supply and grounds are interleaved to increase the capacitance and alleviate the power noise through the power delivery network (PDN) in the construction of the four-element voltage regulator module along with the on-chip capacitor and the specific power–ground layers. Modifying the layout scheme in the PDN with reasonable decoupling capacitance can lead to an additional 1.4 times improvement in the eye height over the original design.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"159-168"},"PeriodicalIF":0.0,"publicationDate":"2024-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142645479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Dual-Stripline Configuration for High-Density Routing in Chiplet Interconnects 用于 Chiplet 互连中高密度路由的双干线配置

IEEE Transactions on Signal and Power Integrity Pub Date : 2024-10-01 DOI: 10.1109/TSIPI.2024.3471470

Shekar Geedimatla;Jayaprakash Balachandran;Midhun Vysakham;Srinivas Venkataraman;Shalabh Gupta

引用次数: 0

Ultrawideband Power-Noise Suppression Based on Lossy Capacitors With Low-Frequency Stopband Enhancement for Digital Systems 基于有损电容器的超宽带功率噪声抑制与数字系统的低频阻带增强功能

IEEE Transactions on Signal and Power Integrity Pub Date : 2024-08-14 DOI: 10.1109/TSIPI.2024.3442986

Yingfeng Ding;Mu-Shui Zhang;Yufang Xu;Haopeng Feng;Zixin Wang

引用次数: 0

Modeling of a Voltage Regulator Module for Power Integrity: Power Supply Induced Jitter 电源完整性稳压器模块建模：电源引起的抖动

IEEE Transactions on Signal and Power Integrity Pub Date : 2024-06-19 DOI: 10.1109/TSIPI.2024.3416088

Junho Joo;Daniel L. Commerou;Hayden Huang;Chun-Yi Yeh;Jiaming Kang;Hank Lin;Bin-Chyi Tseng;Chulsoon Hwang

{"title":"Modeling of a Voltage Regulator Module for Power Integrity: Power Supply Induced Jitter","authors":"Junho Joo;Daniel L. Commerou;Hayden Huang;Chun-Yi Yeh;Jiaming Kang;Hank Lin;Bin-Chyi Tseng;Chulsoon Hwang","doi":"10.1109/TSIPI.2024.3416088","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3416088","url":null,"abstract":"This article analyzes different methods for modeling a buck regulator among the variety of voltage regulator modules from the perspective of power integrity and assesses the accuracy of power supply induced jitter (PSIJ) predictions for each buck regulator model. To compare the buck regulator modeling approaches, methods for conventional passive component modeling and behavior modeling are introduced. Four different buck regulator models are compared with measurements in terms of time-domain voltage ripple and nonlinearity. Then, each model is applied to a simulation-based system-level PSIJ prediction setup to quantify the accuracy of the buck regulator models from the perspective of PSIJ. A printed circuit board with an inverter chain powered by an external buck regulator is selected as the device under test. In the presence of power supply fluctuations due to load current injection on the buck regulator, the time interval error of the inverter is measured. The measured peak-to-peak jitter is then reproduced by various simulation setups with the different buck regulator modeling methods. Finally, the PSIJ simulation accuracy is investigated for each buck regulator model.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"110-125"},"PeriodicalIF":0.0,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141494828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel Vertical Conductive Structure for Printed Circuit Boards and its Scalable Model 用于印刷电路板的新型垂直导电结构及其可扩展模型

IEEE Transactions on Signal and Power Integrity Pub Date : 2024-04-19 DOI: 10.1109/TSIPI.2024.3391210

Junyong Park;Chaofeng Li;Eddie Mok;Joe Dickson;Joan Tourné;Aritharan Thurairajaratnam;DongHyun Kim

{"title":"A Novel Vertical Conductive Structure for Printed Circuit Boards and its Scalable Model","authors":"Junyong Park;Chaofeng Li;Eddie Mok;Joe Dickson;Joan Tourné;Aritharan Thurairajaratnam;DongHyun Kim","doi":"10.1109/TSIPI.2024.3391210","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3391210","url":null,"abstract":"This article proposes a new vertical conductive structure (VeCS) to replace the general via structure for signal connection on printed circuit boards (PCBs). Vias have been widely used as interconnects for in-between layers in PCBs. However, vias have limitations due to their discontinuous characteristic impedance. The VeCS consists of a conductive structure shielded vertically by a metal structure, which provides impedance control. Thus, the VeCS has the constant characteristic impedance that can get better signal integrity for the high-speed channel than the general via structure. This article also proposes a scalable 3-D electromagnetic simulation model of the VeCS for signal integrity analysis. Simulated annealing and linear regression revealed that the scalable model accurately represents the VeCS. The electrical performances of a VeCS and a via were compared up to 70 GHz. The measured insertion losses at 70 GHz for the VeCS and the via were 35 dB and 70 dB, respectively, because PCB vias exhibit significant reflection loss above 10 GHz. In conclusion, this article proposes a novel vertical interconnection for PCBs.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"67-74"},"PeriodicalIF":0.0,"publicationDate":"2024-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140880769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Bandpass NGD Analysis of PCB Folded Li-Shape Trace 带通 NGD 分析 PCB 折叠李形轨迹

IEEE Transactions on Signal and Power Integrity Pub Date : 2024-04-19 DOI: 10.1109/TSIPI.2024.3391212

Fayu Wan;Hongchuan Jia;Blaise Ravelo

引用次数: 0

Near-Field Coupling Analysis of Flexible Printed Circuit Boards 柔性印刷电路板的近场耦合分析

IEEE Transactions on Signal and Power Integrity Pub Date : 2024-03-30 DOI: 10.1109/TSIPI.2024.3406267

Yang Liu;Yuwei Luo;Zhifei Xu;Xiuqin Chu;Jun Wang;Kai-Da Xu

引用次数: 0

Investigation of Voltage Regulator Module (VRM)-Induced Noise to High-Speed Signals With VRM via Design Factors 通过设计因素调查稳压器模块（VRM）对高速信号产生的噪声

IEEE Transactions on Signal and Power Integrity Pub Date : 2024-03-29 DOI: 10.1109/TSIPI.2024.3407030

Junho Joo;Manish K. Mathew;Arun Chada;Soumya Singh;Seema PK;Bhyrav Mutnury;DongHyun Kim

{"title":"Investigation of Voltage Regulator Module (VRM)-Induced Noise to High-Speed Signals With VRM via Design Factors","authors":"Junho Joo;Manish K. Mathew;Arun Chada;Soumya Singh;Seema PK;Bhyrav Mutnury;DongHyun Kim","doi":"10.1109/TSIPI.2024.3407030","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3407030","url":null,"abstract":"As the complexity of server platforms increases, the noise produced by switching voltage regulator modules (VRMs) is more likely to be coupled to nearby high-speed traces. This study aims to investigate the mechanism of noise coupling between the noise generated by a VRM and a high-speed signal trace, as well as to evaluate various noise-reduction methods. A VRM's rapid switching of field effect transistors generates an unintentional coupling region that primarily injects noise into high-speed traces routed in the inner signal layers of the printed circuit boards (PCBs) in server platforms. To analyze various VRM noise coupling mechanisms in practical high-speed channels, a simplified PCB design based on a high-speed server platform is designed and fabricated. In addition, case studies are conducted under various conditions to validate the most efficient VRM noise coupling reduction method by both simulation and measurement. Finally, various design factors that influence VRM noise coupling are evaluated to propose guidelines for high-speed channel designers. This study presents the first comprehensive analysis of different noise coupling mechanisms and an IR drop aware guideline to reduce noise in dense high-speed systems containing a VRM.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"97-109"},"PeriodicalIF":0.0,"publicationDate":"2024-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141319673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Perturbed Pin Map Design for Low Differential Crosstalk in 112 Gb/s PAM4 Applications 在 112 Gb/s PAM4 应用中实现低差分串扰的扰动引脚图设计

IEEE Transactions on Signal and Power Integrity Pub Date : 2024-03-10 DOI: 10.1109/TSIPI.2024.3399099

Mu-Shui Zhang;Yingfeng Ding;Zixin Wang

{"title":"Perturbed Pin Map Design for Low Differential Crosstalk in 112 Gb/s PAM4 Applications","authors":"Mu-Shui Zhang;Yingfeng Ding;Zixin Wang","doi":"10.1109/TSIPI.2024.3399099","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3399099","url":null,"abstract":"As the wired communication data rate increases up to 112 Gb/s and even higher, the differential crosstalk from neighboring pairs becomes much more serious and could significantly deteriorate signal integrity. In this article, a perturbed pin map design method is proposed to reduce the differential crosstalk for 112 Gb/s four-level pulse amplitude modulation applications. Three physical parameters, the distance of two signal pins in a pair, the angle of two adjacent signal pairs, and the positions of surrounding ground vias, are perturbed for maximum crosstalk reduction. Without changing the signal-to-ground ratio and area per differential pair, the proposed pin map patterns can significantly mitigate the total differential crosstalk in via connection field, by both common-mode cancelation enhancement of signal vias and shielding effect improvement of ground vias through perturbation. Numerical examples are performed to verify the validity of crosstalk reduction in both square and triangular pin arrays. Finally, the effect of perturbation amplitude on crosstalk reduction is analyzed; it is shown that differential crosstalk decreases fast when the perturbed offset is smaller than 2\u0000<italic>r</i>\u0000 (\u0000<italic>r</i>\u0000 is the radius of balls), and it becomes slow when the perturbed offset is larger than \u0000<italic>2r</i>\u0000. Compared with the nonperturbed square and triangular patterns, the integrated crosstalk noises of the perturbed patterns are reduced by 70.62% and 68.72%, respectively, at 112 Gb/s, and the insertion loss to crosstalk ratios are averagely increased by 11 dB and 8 dB, respectively, up to 40 GHz, with a perturbed offset of 2\u0000<italic>r</i>\u0000.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"85-96"},"PeriodicalIF":0.0,"publicationDate":"2024-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141245180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0