IEEE Transactions on Signal and Power Integrity最新文献

{"title":"Design and Verification of Wired Channels Beyond 100 Gbps","authors":"Francesco de Paulis;Richard Mellitz;Luis Boluna;Mike Resso;Rick Rabinovich","doi":"10.1109/TSIPI.2025.3557371","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3557371","url":null,"abstract":"The increase of the data rate beyond 100 Gbps for wired channels, such as the Chip-to-Module interfaces, requires a very careful evaluation and optimization of the transmitter and receiver properties and equalization capabilities based on the specific passive channel of interest. The channel operating margin (COM) methodology offered in the IEEE Standard for Ethernet 802.3 is developed for such purpose. It is adopted in this article to demonstrate how it can be used while paving a rigorous step-by-step procedure for the transmitter characterization and the reliable evaluation of the receiver equalization. A wide range of experiments are carried out to demonstrate the effective applicability of the COM method for optimizing the 100 Gbps four-level pulse amplitude modulation signaling and for pushing the channel design toward the length (and loss) limits.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"109-115"},"PeriodicalIF":0.0,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143856266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IBIS Model Simulation Accuracy Improvement by Including Nonlinear Power Supply Induced Jitter Effect","authors":"Yifan Ding;Randy Wolff;Zhiping Yang;Chulsoon Hwang","doi":"10.1109/TSIPI.2025.3551671","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3551671","url":null,"abstract":"The input/output buffer information specification (IBIS) model is limited in its ability to handle power supply induced jitter. In this article, a direct IBIS switching coefficient modification algorithm that improves IBIS simulation accuracy by including the nonlinear jitter effect is presented. Compared with the previous IBIS-modification algorithms, the new algorithm is more straightforward, as it considers the time-averaged power supply noise effect on both the switching coefficient transition edge and the output transition edge. By addressing the nonlinear jitter, the model is more robust under conditions of significant power supply noise, both in terms of the output waveform shape and jitter estimation. This modification algorithm is implemented on an inverter chain circuit and a realistic double data rate (DDR) model. The performance with dc power noise, ac power noise, and multitone power noise is validated. The new proposed algorithm significantly enhances jitter modeling accuracy, reducing the maximum jitter prediction error from 47.3% to 8.19% in the inverter chain case under complex multitone power noise and from a maximum of 80% to below 20% in the realistic DDR model, compared with the previous algorithm.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"55-64"},"PeriodicalIF":0.0,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143748737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comprehensive Measurement and Cross-Sectional Study of Decoupling Capacitor Interconnect Inductance","authors":"Yifan Ding;Faye Squires;Suho Lee;Albert E. Ruehli;Chulsoon Hwang","doi":"10.1109/TSIPI.2025.3550894","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3550894","url":null,"abstract":"The inductance associated with a decoupling capacitor (decap) is represented by its equivalent series inductance (ESL). However, the supplier specified ESL model pertains to a specific physical mounting situation. When mounted on printed circuit board, the datasheet ESL values do not accurately reflect the actual inductance, because of the mounting method and coupling with nearby structures, including connections to return planes through traces and vias. This inductance, <inline-formula><tex-math>${{bm{L}}_{mathbf{above}}}$</tex-math></inline-formula>, is influenced by the decap's connection pattern. Although larger package capacitors are generally assumed to lead to higher loop inductance, our measurements indicated that larger capacitors do not necessarily result in higher <inline-formula><tex-math>${{bm{L}}_{mathbf{above}}}$</tex-math></inline-formula>. The inner geometry of the capacitor and mounting structure was found to significantly influence <inline-formula><tex-math>${{bm{L}}_{mathbf{above}}}$</tex-math></inline-formula>. This study examined the effects of inner geometry on decap inductance, validated through extensive simulations and measurements. <inline-formula><tex-math>${{bm{L}}_{mathbf{above}}}$</tex-math></inline-formula> measurements for 31 types of decaps across four package sizes (0402 to 1206), with six samples tested per capacitor type, revealed overlapping inductance across sizes. Cross-sectional measurements indicated the exact electrode geometry. The determined geometry showed strong correlations between simulated and measured <inline-formula><tex-math>${{bm{L}}_{mathbf{above}}}$</tex-math></inline-formula> results, thus supporting the investigation of the effects of inner geometry on inductance. The relationship between <inline-formula><tex-math>${{bm{L}}_{mathbf{above}}}$</tex-math></inline-formula> and placement orientation was additionally examined.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"46-54"},"PeriodicalIF":0.0,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143748840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Hybrid Deep-Belief and Knowledge-Based Neural Network for Efficient Prediction of Jitter in the Presence of Multiple PDN Noise Sources","authors":"Ahsan Javaid;Ramachandra Achar;Jai Narayan Tripathi","doi":"10.1109/TSIPI.2025.3550155","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3550155","url":null,"abstract":"In this article, an efficient approach is developed to predict the jitter in the presence of multiple noise sources, such as power supply noise, ground bounce noise as well as input data noise in diverse power delivery modules by combining the knowledge-based neural network with the deep belief neural network. The proposed hybrid neural network achieves reasonable accuracy while providing for efficient training using input data obtained from both analytical closed-form expressions as well as a circuit simulator. The proposed model can also handle varying inputs without retraining the network's parameters. In order to optimize the training dataset, instead of using the random dataset, a new configuration with a mixed dataset (with a combination of uniformly distributed data as well as randomly distributed data) is proposed. Their performance along with different types of energy models is also investigated.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"33-45"},"PeriodicalIF":0.0,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143748841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Novel Far-End Crosstalk Noise Canceling Structure With Floating Shape in Memory Module","authors":"Seungjin Lee;Jonghoon J. Kim;Dongyeop Kim;Kyoungsun Kim;Jeonghyeon Cho;Wonhwa Shin","doi":"10.1109/TSIPI.2025.3568775","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3568775","url":null,"abstract":"This article proposes a new structure of floating shape in a dual in-line memory module (DIMM) that can effectively suppress the far-end crosstalk noise. The floating shape located under the gold finger of the DIMM is not connected to any signal line or power/ground planes, but overlaps multiple signal lines. This structure can effectively enhance mutual capacitance coupling between signal lines, thereby alleviating the far-end crosstalk noise. For verification, the simulated results of the far-end crosstalk voltage and eye diagram are compared. The proposed structure shows that the far-end crosstalk voltage is greatly reduced from 44.8 to 24.0 mV and the eye diagram is improved by about 17% for both eye height and width. System-level experiments also prove the effectiveness of the proposed design.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"132-136"},"PeriodicalIF":0.0,"publicationDate":"2025-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144322997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fine-Grained Modeling and Evaluation of 3-D Power Distribution Networks in Logic-on-Memory Stacking Architecture","authors":"Ang Li;Pengyu Liu;Zizheng Dong;Jinhao Li;Jianfei Jiang;Weijia Zhu;Naifeng Jing;Qin Wang","doi":"10.1109/TSIPI.2025.3548965","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3548965","url":null,"abstract":"With the escalating computing power demands in artificial intelligence-generated content and other applications, the three-dimensional (3-D) stacking technology has effectively broken through the bottleneck of Moore's law and become the primary choice for high-performance chip packaging technology. Especially in the logic-on-memory (LoM) scenario with strong industrial feasibility, the 3-D stacking process fully leverages its advantages of extremely high interconnection density and low communication delay, making it well-suited for addressing the bandwidth expansion challenges under the “memory wall” bottleneck. Nevertheless, the heightened integration level and reduced power consumption requirements of the LoM architecture have introduced significant challenges to the power supply of stacking chips. Current EDA tools lack the capability to rapidly and effectively explore the optimal design of LoM power distribution networks (PDNs), and existing SPICE-type 3-D PDN analysis models often encounter challenges with oversimplified modeling approach and idealized power analysis, rendering them unsuitable for LoM structures, such as near-memory computing and high-bandwidth processors in computing/memory stacking scenarios. In this work, we propose for the first time a fine-grained 3-D PDN analysis modeling approach designed for LoM stacking architecture. Our modeling method comprehensively accounts for the power supply characteristics within the stacking architectures, and implements fine-grained segmentation and modeling of the full-chip PDN based on the estimated area, power consumption, and backend-of-line dimensions, allowing for rapid and accurate evaluation of power integrity (PI) across different PDN design schemes before the physical design stage. Furthermore, we explore the optimal 3-D LoM PDN design across various physical design spaces, including multilayer PDN connection schemes, metal layer configuration, and through-silicon via placement density. The final analysis result is applied to guide the practical physical design of the LoM PDN, highlighting the significance of our modeling approach in 3-D chip PI analysis and 3-D PDN design optimization.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"65-80"},"PeriodicalIF":0.0,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143792932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analytical Modeling of Eye Diagram for Jitter Estimation in Presence of Ground Bounce","authors":"Anuj Kumar;Jai Narayan Tripathi","doi":"10.1109/TSIPI.2025.3545383","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3545383","url":null,"abstract":"This work presents an analytical model for an eye diagram to estimate jitter. The contribution is embodied in the development of a specialised analytical model to accurately estimate jitter caused by ground-bounce noise in complementary metal-oxide-semiconductor inverter circuits. This work is highly relevant in the area of high-speed very large-scale integrated circuit design as it provides significant theoretical contributions for the estimation of jitter and assessment of signal quality using eye diagrams. The input–output relationship has been utilized to derive rising transition edges. Building upon this derivation, analytical equations have been developed to predict jitter for output transitions considering falling ramp inputs in the inverter. The eye diagram model is illustrated after integrating the rising transition edges concurrent with the falling transition edges. The robust analytical framework yields consistent results, aligning closely with simulated predictions and the physical measurements using HEX inverter ICs provide validation to the proposed modeling. The comprehensive study affirms notable accuracy in the comparison of analytical, simulated, and experimental findings.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"24-32"},"PeriodicalIF":0.0,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Electromagnetic Compatibility Society Information","authors":"","doi":"10.1109/TSIPI.2025.3533060","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3533060","url":null,"abstract":"","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10854552","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2024 Index IEEE Transactions on Signal and Power Integrity Vol. 3","authors":"","doi":"10.1109/TSIPI.2025.3534910","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3534910","url":null,"abstract":"","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10854991","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Accurate and Broadband Three-Phase Motor Modeling Methodology Based on Vector Fitting","authors":"Junyong Park;Yuandong Guo;Hongseok Kim;Jun Fan;DongHyun Kim","doi":"10.1109/TSIPI.2025.3531840","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3531840","url":null,"abstract":"An accurate and broadband modeling methodology for a typical permanent magnet synchronous motor (PMSM) in a vehicular three-phase braking system is proposed for the first time to improve the accuracy of induced electromagnetic interference (EMI) in three-phase motor systems. The proposed model is verified by measurement from dc to 120 MHz both in common- and differential-mode current measurement of the three-phase motor under study. The proposed model can be used in analysis and prediction of the electromagnetic noise of the motor-drive braking system. The model can also be incorporated into frequency- and time-domain simulations. The modeling approach is based on the vector fitting technique of measured three-phase motor impedance and <italic>S</i>-parameter, where the three-phase PMSM is modeled as a multiport device. In addition, the proposed modeling method for the PMSM can be used for different types of three-phase motors for EMI simulations and analysis.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"81-87"},"PeriodicalIF":0.0,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143792935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}