IEEE Transactions on Signal and Power Integrity最新文献_第2页

Adaptive Frequency Sweep Using Query by Committee: A Comparative Study With Vector Fitting-Based AFS 基于委员会查询的自适应频率扫描：与基于向量拟合的AFS的比较研究

IEEE Transactions on Signal and Power Integrity Pub Date : 2026-01-01 Epub Date: 2026-09-10 DOI: 10.1109/TSIPI.2026.3729930

Akash;Sayantan Das;Dipanjan Gope

{"title":"Adaptive Frequency Sweep Using Query by Committee: A Comparative Study With Vector Fitting-Based AFS","authors":"Akash;Sayantan Das;Dipanjan Gope","doi":"10.1109/TSIPI.2026.3729930","DOIUrl":"https://doi.org/10.1109/TSIPI.2026.3729930","url":null,"abstract":"Three dimensional full wave simulations are computationally expensive for applications, such as signal integrity, microwave design, electromagnetic compatibility design, etc., that require responses over dense frequency samples. Adaptive frequency sweep (AFS) is a widely employed technique to mitigate this issue. However, conventional AFS methods may suffer from false convergence and unnecessarily increased runtime, which arises due to the selection of noninformative points. This article proposes a query by committee based-AFS that employs a diverse set of surrogate models to enhance the decision-making for faster convergence and accuracy. This approach exploits a standard deviation-based disagreement among the different members of a committee, which targets the region with high uncertainty, and hence adds better information for model order reduction. The efficiency of the proposed method is demonstrated through several multiport testcases, including a 3-stub low-pass filter, and is compared against the conventional vector fitting-based AFS method. The accuracy of both methods is compared using norm-based error metrics and dynamic time warping with respect to the discrete frequency sweep. Numerical results show that the proposed method achieves good accuracy with significantly fewer frequency samples, and hence reduces the computational cost.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"192-205"},"PeriodicalIF":0.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149131534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Sixth-Order-Based Gaussian Kernel LMS and Optimized Fractional-Order Control for Power Quality Enhancement 基于六阶高斯核LMS和优化分数阶控制的电能质量增强

IEEE Transactions on Signal and Power Integrity Pub Date : 2026-01-01 Epub Date: 2026-07-01 DOI: 10.1109/TSIPI.2026.3708791

Prashant Kumar;Sabha Raj Arya;Shailendra Kumar

{"title":"Sixth-Order-Based Gaussian Kernel LMS and Optimized Fractional-Order Control for Power Quality Enhancement","authors":"Prashant Kumar;Sabha Raj Arya;Shailendra Kumar","doi":"10.1109/TSIPI.2026.3708791","DOIUrl":"https://doi.org/10.1109/TSIPI.2026.3708791","url":null,"abstract":"This work integrates the sixth-order Gaussian kernel least mean algorithm (SOGKLMA) and an optimized fractional order proportional–integral–derivative (FOPID) controller to enhance the electrical power quality (EPQ). To address the EPQ issues, the first key objective is to extract the fundamental quantity from the disturbed grid by employing (SOGKLMA). An SOGKLMA enhances dynamic performance through higher order filtering that effectively adapts to excess errors by incorporating a Gaussian kernel function. This accurately estimates the fundamental component to maintain the load voltage at its predefined value, thereby estimating reference load voltage generation and enabling faster convergence under severe transients. Moreover, an FOPID controller is employed to maintain the DC-link voltage at 300 V. The effectiveness of FOPID is validated by integrating the objective function, integral time square error (ITSE), with a comparative study. The artificial protozoa optimizer (APO)-based FOPID confirms superior performance compared with the recently developed Beluga whale optimizer (BWO), yielding a lower ITSE of 0.001528 compared with 0.044899. The simulation responses of the proposed APO-tuned FOPID ensure its supremacy by comparing with a recently developed approach called the BWO with an enhanced transient response, including lessening the maximum overshoot (Mp = 5.7%), undershoot (Us = 3.44%), settling time (Ts = 0.15s), and steady-state (<italic>ess = 0.678%). Finally, system robustness is examined through experimentation with a laboratory-scaled-down DVR prototype.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"123-131"},"PeriodicalIF":0.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Practical Approaches to Quantifying Intrapair Skew Impact via Insertion Loss Deviation 用插入损耗偏差量化对内偏影响的实用方法

IEEE Transactions on Signal and Power Integrity Pub Date : 2026-01-01 Epub Date: 2026-08-12 DOI: 10.1109/TSIPI.2026.3723353

David Nozadze;Zurab Kiguradze;Amendra Koul;Sayed Ashraf Mamun;Mike Sapozhnikov

{"title":"Practical Approaches to Quantifying Intrapair Skew Impact via Insertion Loss Deviation","authors":"David Nozadze;Zurab Kiguradze;Amendra Koul;Sayed Ashraf Mamun;Mike Sapozhnikov","doi":"10.1109/TSIPI.2026.3723353","DOIUrl":"https://doi.org/10.1109/TSIPI.2026.3723353","url":null,"abstract":"The surge in AI workloads and escalating data center requirements have created demand for ultra-high-speed interconnects exceeding 200 Gb/s. As unit intervals shrink, even a few picoseconds of intrapair skew can significantly degrade serializer–deserializer (SerDes) performance. To quantify the impact of intrapair skew, conventional time-domain methods are often unreliable for coupled interconnects due to skew variations across voltage levels, while frequency-domain approaches frequently fail to address reciprocity and symmetry issues. This can result in channels that meet skew specifications in one direction but not the other, despite the inherently reciprocal nature of skew impact. To address these limitations, we introduce two new reciprocal parameters for quantifying intrapair skew effects: skew-induced insertion loss deviation (SILD) and its complementary figure of merit (FOM_SILD). Measurements conducted using 224-Gb/s SerDes IP and a variety of channels with different intrapair skews demonstrate a strong correlation between FOM_SILD and bit error rate (BER). Results show that when FOM_SILD is below 0.2–0.3 dB, BER remains stable, indicating minimal signal integrity degradation; however, BER increases noticeably as FOM_SILD exceeds 0.3 dB. Statistical analysis across more than 3000 high-speed twinax cables reveals that the majority exhibit FOM_SILD values less than 0.1 dB, underscoring the practical relevance of the proposed metrics for high-speed interconnect assessment.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"171-178"},"PeriodicalIF":0.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Perforated Ground Plane Design for Mitigating Mode Conversion in the High-Speed Differential Channels of a Die-to-Die Interface 用于减少模对模接口高速差分通道模式转换的穿孔接地面设计

IEEE Transactions on Signal and Power Integrity Pub Date : 2026-01-01 Epub Date: 2026-06-18 DOI: 10.1109/TSIPI.2026.3705083

Hyunwoo Kim;Seunghun Ryu;Sanguk Lee;Seonghi Lee;Dongryul Park;Jinwook Lee;Seungyoung Ahn

{"title":"Perforated Ground Plane Design for Mitigating Mode Conversion in the High-Speed Differential Channels of a Die-to-Die Interface","authors":"Hyunwoo Kim;Seunghun Ryu;Sanguk Lee;Seonghi Lee;Dongryul Park;Jinwook Lee;Seungyoung Ahn","doi":"10.1109/TSIPI.2026.3705083","DOIUrl":"https://doi.org/10.1109/TSIPI.2026.3705083","url":null,"abstract":"In this article, we present a perforated ground plane design methodology that effectively mitigates mode conversion in high-speed differential channels. The proposed design utilizes perforated ground unit cells (PGUCs) with a symmetric geometry and a periodic arrangement to provide a uniform return current path for the channels, thereby effectively alleviating the characteristic impedance mismatch. In addition, mode conversion is analyzed using the universal chiplet interconnect express as a representative die-to-die interface. The results demonstrate consistent and superior performance of approximately <inline-formula><tex-math>$-$</tex-math></inline-formula>70 dB across various channel configurations, compared to conventional designs that exhibit variations from <inline-formula><tex-math>$-$</tex-math></inline-formula>68.5 to <inline-formula><tex-math>$-$</tex-math></inline-formula>43 dB, depending on the channel position. Furthermore, the proposed design is comprehensively validated through common-mode current, differential skew, and transient step-response analyses, confirming that the symmetric PGUC geometry maintains uniform mode conversion performance while preserving signal integrity of the differential channel.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"93-96"},"PeriodicalIF":0.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Estimation of Jitter Using Knowledge-Based Bidirectional Mamba Architecture for XDR Systems 基于知识的双向Mamba结构的XDR系统抖动估计

IEEE Transactions on Signal and Power Integrity Pub Date : 2026-01-01 Epub Date: 2026-06-16 DOI: 10.1109/TSIPI.2026.3702577

Ahsan Javaid;Ramachandra Achar;Jai Narayan Tripathi

引用次数: 0

A Transformer-Based IBIS-AMI Modeling Method for High-Speed Nonlinear Buffers 基于变压器的高速非线性缓冲器IBIS-AMI建模方法

IEEE Transactions on Signal and Power Integrity Pub Date : 2026-01-01 Epub Date: 2026-07-03 DOI: 10.1109/TSIPI.2026.3709804

Seonghi Lee;Sanguk Lee;Zhiping Yang;Seungyoung Ahn;Chulsoon Hwang

{"title":"A Transformer-Based IBIS-AMI Modeling Method for High-Speed Nonlinear Buffers","authors":"Seonghi Lee;Sanguk Lee;Zhiping Yang;Seungyoung Ahn;Chulsoon Hwang","doi":"10.1109/TSIPI.2026.3709804","DOIUrl":"https://doi.org/10.1109/TSIPI.2026.3709804","url":null,"abstract":"A transformer-based IBIS-AMI modeling method for high-speed nonlinear buffers is proposed, capable of capturing complex nonlinear buffer behavior directly from bit-level waveforms while remaining fully compatible with standard IBIS-AMI workflows. As high-speed interfaces become increasingly complex, conventional IBIS models face growing difficulty in capturing detailed nonlinear characteristics, while existing neural-network-based models cannot be used directly within IBIS-AMI simulations. To address these limitations, the proposed model directly processes waveform sequences and is integrated into the IBIS-AMI workflow without modifying the existing procedure. Global information representing the operating condition is added to the input embedding, and past-chunk data are embedded into the decoder to suppress discontinuities at chunk boundaries. The model is trained and evaluated on nonlinear circuit cases, where the predicted waveforms closely match transistor-level simulation results across all tested conditions, with eye-width and eye-height deviations remaining within approximately 5%. The proposed approach maintains full compatibility with the IBIS-AMI framework and provides practical value for high-speed interface design and analysis.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"113-122"},"PeriodicalIF":0.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hybrid Techniques for Power Noise Suppression on Multichip Packages 多芯片封装中功率噪声抑制的混合技术

IEEE Transactions on Signal and Power Integrity Pub Date : 2026-01-01 Epub Date: 2026-04-02 DOI: 10.1109/TSIPI.2026.3680416

Qing Zhou;Jinsong Hu;Xiao Hu

{"title":"Hybrid Techniques for Power Noise Suppression on Multichip Packages","authors":"Qing Zhou;Jinsong Hu;Xiao Hu","doi":"10.1109/TSIPI.2026.3680416","DOIUrl":"https://doi.org/10.1109/TSIPI.2026.3680416","url":null,"abstract":"Power-noise coupling among IPs is a common challenge in multichip-package (MCP) design. Voltage droop and power noise generated by an aggressor chiplet can couple to a victim chiplet through the power delivery network (PDN) on a shared power rail, particularly when the victim contains high-speed IP with stringent noise requirements. In conventional designs, coupling can be mitigated through PDN codesign and by adding board-level filtering for each chiplet. However, when the board design is frozen, noise observed on sensitive IP can become a gating item for package tape-out. This article presents three package- and die-level approaches for late-stage reduction of power-noise coupling between an aggressor and a victim. The first approach isolates PDN paths by partitioning the socket power-pin connectivity. The second approach integrates an embedded inductor to implement an in-package low-pass filter. The third approach optimizes on-die decoupling capacitance and effective resistance to attenuate high-frequency noise at the victim. Design and simulation were completed within two weeks of tape-out, demonstrating a 75% reduction in victim-rail noise.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"53-58"},"PeriodicalIF":0.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147696157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Prelayout Design Synthesis for Decap Placement in Multipower Domains Using Multiagent Reinforcement Learning 基于多智能体强化学习的多功率域Decap预布局设计综合

IEEE Transactions on Signal and Power Integrity Pub Date : 2026-01-01 Epub Date: 2026-08-26 DOI: 10.1109/TSIPI.2026.3727926

Haran Manoharan;Hanfeng Wang;Jingnan Pan;Xu Gao;Bobi Shi;Jianmin Zhang;Chulsoon Hwang

{"title":"Prelayout Design Synthesis for Decap Placement in Multipower Domains Using Multiagent Reinforcement Learning","authors":"Haran Manoharan;Hanfeng Wang;Jingnan Pan;Xu Gao;Bobi Shi;Jianmin Zhang;Chulsoon Hwang","doi":"10.1109/TSIPI.2026.3727926","DOIUrl":"https://doi.org/10.1109/TSIPI.2026.3727926","url":null,"abstract":"In printed circuit boards supporting modern systems-on-chip (SoCs), ensuring robust power delivery across multiple voltage domains is essential for meeting performance, energy efficiency, and reliability requirements. Decoupling capacitors (decaps) are critical for maintaining voltage stability and suppressing power noise, but determining their optimal placement, quantity, and values remains a complex challenge especially in the early, prelayout design phase where physical constraints are not yet finalized. This article presents a novel prelayout synthesis framework for decap optimization using multiagent reinforcement learning . Each power pin is represented by a stateless agent that proposes candidate placements beneath the IC, while a centralized controller coordinates all agents and leverages a Transformer-based policy network to determine the optimal decap values and minimize the total number used. The framework enables simultaneous optimization across multiple power domains making it highly suitable for early-stage design. The method is validated on a real-world mobile SoC with 20 power domains, where it generates impedance-compliant, space-efficient decap configurations in under 15 min, significantly reducing design effort.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"179-191"},"PeriodicalIF":0.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149033558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reverse and Adaptive T-Coil Design for Wireline Receiver Input Matching 有线接收机输入匹配的反向自适应t型线圈设计

IEEE Transactions on Signal and Power Integrity Pub Date : 2026-01-01 Epub Date: 2026-07-16 DOI: 10.1109/TSIPI.2026.3714423

Jerry Ho;Yu-Chuan Lin;Hen-Wai Tsao

{"title":"Reverse and Adaptive T-Coil Design for Wireline Receiver Input Matching","authors":"Jerry Ho;Yu-Chuan Lin;Hen-Wai Tsao","doi":"10.1109/TSIPI.2026.3714423","DOIUrl":"https://doi.org/10.1109/TSIPI.2026.3714423","url":null,"abstract":"This article presents the characteristics of the reverse T-coil and compares them with those of the classic T-coil, considering both bridged and nonbridged configurations, with an emphasis on receiver input matching. A comprehensive mathematical framework is developed, and parameter sweep analysis is conducted to explore the potential of the reverse T-coil. Furthermore, we demonstrate a contour-based design procedure for input matching networks that employ a reverse T-coil for equalization. To adaptively adjust the gain boost provided by the reverse T-coil according to different channels, we augment the reverse T-coil with a termination-splitting technique, forming what we refer to as the adaptive T-coil. When jointly optimized with continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE), the adaptive T-coil boosting improves jitter tolerance from 0.11 UI with CTLE and DFE alone to 0.23 UI, corresponding to a 0.12 UI enhancement. This performance exceeds the PCIe Gen5 jitter tolerance requirement of 0.1 UI, providing sufficient margin. The improvement is achieved without additional area or power penalty in a PCIe Gen5 receiver operating at 32 Gb/s over a channel with 38 dB loss, as confirmed by silicon measurements under a bit error rate of 10−12.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"141-153"},"PeriodicalIF":0.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148748322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of Filtering Cable Using Coupled Suspended Circuit With Dumbbell-Shaped Defected Conductor Layer and Capacitors 带哑铃形缺陷导体层和电容的耦合悬浮滤波电缆设计

IEEE Transactions on Signal and Power Integrity Pub Date : 2026-01-01 Epub Date: 2025-06-12 DOI: 10.1109/TSIPI.2025.3579350

Yu-Nan Han;Shuang-Qing Xiong;Guang Yang;Chao-Yang Wu;Chun-Yue Cheng

{"title":"Design of Filtering Cable Using Coupled Suspended Circuit With Dumbbell-Shaped Defected Conductor Layer and Capacitors","authors":"Yu-Nan Han;Shuang-Qing Xiong;Guang Yang;Chao-Yang Wu;Chun-Yue Cheng","doi":"10.1109/TSIPI.2025.3579350","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3579350","url":null,"abstract":"This article presents a filtering cable designed to control electromagnetic interference (EMI) by enclosing the power line with a coupled suspended circuit (CSC), which consists of a defected conductor layer (DCL) and surface-mounted capacitors. An equivalent circuit model for the filtering cable is developed, considering the transfer of current distribution from the DCL to an equivalent microstrip filter and extracting the circuit model of its discontinuity modules. The filtering cable achieves interference suppression exceeding 11 dB at 21.49 MHz with a capacitance of 1.36 nF for a single dumbbell-shaped defected structure (35 mm length on a transmission dielectric diameter of 24.3 mm), and 15.8 dB at 39.52 MHz with a capacitance of 400 pF. Furthermore, for a dumbbell-shaped defected structure length of 600 mm and a capacitance of 9.82 nF, the proposed filtering cable achieves interference suppression exceeding 5.98 dB at 2.23 MHz for a single resonator and 9.26 dB at 2.27 MHz for two cascaded resonators. Simulation and measurement results demonstrate the effective EMI suppression achieved by the proposed filtering cable, which can be further adjusted by modifying the areas of the dumbbell-shaped defected structure, the capacitors, and the cascading of resonators.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"206-216"},"PeriodicalIF":0.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149131535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0