IBIS Model Simulation Accuracy Improvement by Including Nonlinear Power Supply Induced Jitter Effect

Abstract

The input/output buffer information specification (IBIS) model is limited in its ability to handle power supply induced jitter. In this article, a direct IBIS switching coefficient modification algorithm that improves IBIS simulation accuracy by including the nonlinear jitter effect is presented. Compared with the previous IBIS-modification algorithms, the new algorithm is more straightforward, as it considers the time-averaged power supply noise effect on both the switching coefficient transition edge and the output transition edge. By addressing the nonlinear jitter, the model is more robust under conditions of significant power supply noise, both in terms of the output waveform shape and jitter estimation. This modification algorithm is implemented on an inverter chain circuit and a realistic double data rate (DDR) model. The performance with dc power noise, ac power noise, and multitone power noise is validated. The new proposed algorithm significantly enhances jitter modeling accuracy, reducing the maximum jitter prediction error from 47.3% to 8.19% in the inverter chain case under complex multitone power noise and from a maximum of 80% to below 20% in the realistic DDR model, compared with the previous algorithm.