{"title":"混合信号电子器件在10kHz至5MHz频率范围内对电源干扰的抗扰度测试","authors":"Federico Sordi;Leonardo Vignoli;Lorenzo Capineri;Carlo Carobbi","doi":"10.1109/TSIPI.2022.3225511","DOIUrl":null,"url":null,"abstract":"A method is presented to test the immunity of mixed signal (digital and analog) electronics to power supply disturbances in the frequency range between 10 and 5 MHz, as those originating from switched mode power supplies. An example of application of the method to a serializer/deserializer integrated circuit is illustrated. For these electronic devices, the power supply noise can critically affect performance. The SerDes is hosted by an evaluation board supplied by an external power module (PM). An adhoc disturbance source and coupling/Decoupling network (CDN) have been designed to couple a disturbance of significant amplitude to the power supply of the evaluation board while decoupling it from the power module (PM). The radiofrequency mpedance of the bypass network of the evaluation board has been considered for the design of both the disturbance source and the CDN. Details about the architecture and operation of the high-current, broadband and linear power amplifier used for disturbance generation are provided, along with component selection and verification of the CDN. The practical implementation of the test, including a feedback control loop capable of generating the specified disturbance level over the frequency range of interest, is described. Finally, test results are reported in terms of the SerDes bit error rate degradation as a function of disturbance amplitude and frequency.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"170-178"},"PeriodicalIF":0.0000,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Immunity Testing of Mixed Signal Electronics Against Power Supply Disturbances in the Frequency Range From 10 kHz To 5 MHz\",\"authors\":\"Federico Sordi;Leonardo Vignoli;Lorenzo Capineri;Carlo Carobbi\",\"doi\":\"10.1109/TSIPI.2022.3225511\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A method is presented to test the immunity of mixed signal (digital and analog) electronics to power supply disturbances in the frequency range between 10 and 5 MHz, as those originating from switched mode power supplies. An example of application of the method to a serializer/deserializer integrated circuit is illustrated. For these electronic devices, the power supply noise can critically affect performance. The SerDes is hosted by an evaluation board supplied by an external power module (PM). An adhoc disturbance source and coupling/Decoupling network (CDN) have been designed to couple a disturbance of significant amplitude to the power supply of the evaluation board while decoupling it from the power module (PM). The radiofrequency mpedance of the bypass network of the evaluation board has been considered for the design of both the disturbance source and the CDN. Details about the architecture and operation of the high-current, broadband and linear power amplifier used for disturbance generation are provided, along with component selection and verification of the CDN. The practical implementation of the test, including a feedback control loop capable of generating the specified disturbance level over the frequency range of interest, is described. Finally, test results are reported in terms of the SerDes bit error rate degradation as a function of disturbance amplitude and frequency.\",\"PeriodicalId\":100646,\"journal\":{\"name\":\"IEEE Transactions on Signal and Power Integrity\",\"volume\":\"1 \",\"pages\":\"170-178\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Signal and Power Integrity\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/9968134/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Signal and Power Integrity","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/9968134/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Immunity Testing of Mixed Signal Electronics Against Power Supply Disturbances in the Frequency Range From 10 kHz To 5 MHz
A method is presented to test the immunity of mixed signal (digital and analog) electronics to power supply disturbances in the frequency range between 10 and 5 MHz, as those originating from switched mode power supplies. An example of application of the method to a serializer/deserializer integrated circuit is illustrated. For these electronic devices, the power supply noise can critically affect performance. The SerDes is hosted by an evaluation board supplied by an external power module (PM). An adhoc disturbance source and coupling/Decoupling network (CDN) have been designed to couple a disturbance of significant amplitude to the power supply of the evaluation board while decoupling it from the power module (PM). The radiofrequency mpedance of the bypass network of the evaluation board has been considered for the design of both the disturbance source and the CDN. Details about the architecture and operation of the high-current, broadband and linear power amplifier used for disturbance generation are provided, along with component selection and verification of the CDN. The practical implementation of the test, including a feedback control loop capable of generating the specified disturbance level over the frequency range of interest, is described. Finally, test results are reported in terms of the SerDes bit error rate degradation as a function of disturbance amplitude and frequency.