混合信号电子器件在10kHz至5MHz频率范围内对电源干扰的抗扰度测试

Federico Sordi;Leonardo Vignoli;Lorenzo Capineri;Carlo Carobbi
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引用次数: 0

摘要

提出了一种测试混合信号(数字和模拟)电子器件对频率范围在10和5MHz之间的电源干扰的抗扰度的方法,这些干扰源于开关模式电源。示出了将该方法应用于串行器/解串器集成电路的示例。对于这些电子设备,电源噪声会严重影响性能。SerDes由外部电源模块(PM)提供的评估板托管。自组织干扰源和耦合/去耦网络(CDN)已被设计为将显著幅度的干扰耦合到评估板的电源,同时将其与电源模块(PM)去耦。干扰源和CDN的设计都考虑了评估板旁路网络的射频阻抗。提供了用于干扰产生的大电流、宽带和线性功率放大器的架构和操作细节,以及CDN的组件选择和验证。描述了测试的实际实现,包括能够在感兴趣的频率范围内产生指定干扰水平的反馈控制回路。最后,根据作为干扰幅度和频率的函数的SerDes误码率退化来报告测试结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Immunity Testing of Mixed Signal Electronics Against Power Supply Disturbances in the Frequency Range From 10 kHz To 5 MHz
A method is presented to test the immunity of mixed signal (digital and analog) electronics to power supply disturbances in the frequency range between 10 and 5 MHz, as those originating from switched mode power supplies. An example of application of the method to a serializer/deserializer integrated circuit is illustrated. For these electronic devices, the power supply noise can critically affect performance. The SerDes is hosted by an evaluation board supplied by an external power module (PM). An adhoc disturbance source and coupling/Decoupling network (CDN) have been designed to couple a disturbance of significant amplitude to the power supply of the evaluation board while decoupling it from the power module (PM). The radiofrequency mpedance of the bypass network of the evaluation board has been considered for the design of both the disturbance source and the CDN. Details about the architecture and operation of the high-current, broadband and linear power amplifier used for disturbance generation are provided, along with component selection and verification of the CDN. The practical implementation of the test, including a feedback control loop capable of generating the specified disturbance level over the frequency range of interest, is described. Finally, test results are reported in terms of the SerDes bit error rate degradation as a function of disturbance amplitude and frequency.
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