IEEE Transactions on Signal and Power Integrity最新文献_第6页

Signal Integrity Analysis of Neuronal Spike Signal in 3-D Packaging 三维封装中神经元尖峰信号的信号完整性分析

IEEE Transactions on Signal and Power Integrity Pub Date : 2023-03-11 DOI: 10.1109/TSIPI.2023.3275124

Yan Li;Heyuan Yu;Erping Li

{"title":"Signal Integrity Analysis of Neuronal Spike Signal in 3-D Packaging","authors":"Yan Li;Heyuan Yu;Erping Li","doi":"10.1109/TSIPI.2023.3275124","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3275124","url":null,"abstract":"Prompted by the continual advancements in artificial intelligence, the neuromorphic chip based on a spiking neural network (SNN) has attracted considerable attention because of its beneficial architecture of memory computing integration. Unlike traditional artificial neural networks, SNNs process information based on discrete-time spikes. This unique spike signal tends to bring an entire new series of signal integrity (SI) problems in three-dimensional (3-D) packaging. In this article, the resistance–inductance–capacitance–conductance (RLGC) equivalent circuit of through-silicon vias (TSV) and redistribution layer (RDL) structure was modeled in 3-D packaging. Furthermore, the spike SI issues, such as reflection, delay, and loss of spike signals, were also analyzed in 3-D packaging. The results illustrated that the corners between RDL and TSV in 3-D packaging could lead to reflections on the spike signals, resulting in distorted waveforms and increased signal loss. The time delay of the spike signal is only related to the electrical characteristics of the transmission link itself and not to the input signal. In addition, the SI of the spike signal was simulated with possible internal voids as well as the open and short defects in the 3-D packaging. The findings also demonstrated that both open and short defects distort the spike signal's waveform, whereas internal voids almost do not affect the signal. This article presents the first systematic analysis of numerous SI issues of spike signals in 3-D packaging while providing a specific reference for designing neuromorphic chips.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"84-93"},"PeriodicalIF":0.0,"publicationDate":"2023-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67898146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fast PCB Stack-Up Optimization Using Integer Programming 使用整数规划的快速PCB堆叠优化

IEEE Transactions on Signal and Power Integrity Pub Date : 2023-02-23 DOI: 10.1109/TSIPI.2023.3248539

Jiayi He;Ling Zhang;Zurab Kiguradze;Arun Chada;Adam Klivans;Bhyrav Mutnury;Er-Ping Li;Jun Fan

{"title":"Fast PCB Stack-Up Optimization Using Integer Programming","authors":"Jiayi He;Ling Zhang;Zurab Kiguradze;Arun Chada;Adam Klivans;Bhyrav Mutnury;Er-Ping Li;Jun Fan","doi":"10.1109/TSIPI.2023.3248539","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3248539","url":null,"abstract":"This article presents a flexible and efficient methodology to optimize stack-up for multilayer printed circuit boards (PCBs) with enormous search space and various design constraints. PCB stack-up optimization is crucial in high-speed system design to achieve the desired electrical performance while reducing system costs. The stack-up optimization process is labor-intensive and time-consuming for a large number of layers. Moreover, after the optimization process, the electrical performance of a real design, such as the impedance and loss, may deviate from the target design due to manufacturing variations. Estimating the worst cases due to the manufacturing variations, referred to as “corner cases” in this article, is essential for a confident PCB design but challenging since the number of related parameters is large. In this article, PCB stack-up optimization and corner-case searching are addressed and greatly accelerated using the integer programming technique. All constraints are converted to mathematical equalities and inequalities that can be solved rapidly by an integer programming solver to obtain feasible stack-up solutions. After the cross sections of the transmission lines are optimized based on the stack-up design to achieve a target electrical performance, the upper and lower bound of impedance and loss are acquired using integer programming when the design parameters vary in a particular range. The proposed method is verified using multilayer PCB designs with practical constraints and demonstrates its effectiveness and high efficiency.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"32-42"},"PeriodicalIF":0.0,"publicationDate":"2023-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Electromagnetic Compatibility Society Information IEEE电磁兼容性协会信息

IEEE Transactions on Signal and Power Integrity Pub Date : 2023-02-22 DOI: 10.1109/TSIPI.2023.3247617

引用次数: 0

IEEE Transactions on Signal and Power Integrity Information for Authors IEEE作者信号和功率完整性信息汇刊

IEEE Transactions on Signal and Power Integrity Pub Date : 2023-02-22 DOI: 10.1109/TSIPI.2023.3247619

引用次数: 0

PEEC Modeling in 3D IC/Packaging Applications Based on Layered Green's Functions 基于分层Green函数的三维IC/封装应用PEEC建模

IEEE Transactions on Signal and Power Integrity Pub Date : 2023-02-16 DOI: 10.1109/TSIPI.2023.3244893

Biyao Zhao;Siqi Bai;Jun Fan;Brice Achkir;Albert Ruehli

引用次数: 1

Long Short-Term Memory Neural Equalizer 长短期记忆神经均衡器

IEEE Transactions on Signal and Power Integrity Pub Date : 2023-02-06 DOI: 10.1109/TSIPI.2023.3242855

Zihao Wang;Zhifei Xu;Jiayi He;Hervé Delingette;Jun Fan

引用次数: 4

Novel Target-Impedance Extraction Method-Based Optimal PDN Design for High-Performance SSD Using Deep Reinforcement Learning 基于深度强化学习的高性能固态硬盘目标阻抗提取新方法PDN优化设计

IEEE Transactions on Signal and Power Integrity Pub Date : 2023-01-12 DOI: 10.1109/TSIPI.2023.3235310

Jinwook Song;Daniel Hyunsuk Jung;Jaeyoung Shin;Chunghyun Ryu;Youngjun Ko;Sungwoo Jin;Soyoung Jung;Kyungsuk Kim;Youngmin Ku;Jung-Hwan Choi;Sunghoon Chun;Jonggyu Park

{"title":"Novel Target-Impedance Extraction Method-Based Optimal PDN Design for High-Performance SSD Using Deep Reinforcement Learning","authors":"Jinwook Song;Daniel Hyunsuk Jung;Jaeyoung Shin;Chunghyun Ryu;Youngjun Ko;Sungwoo Jin;Soyoung Jung;Kyungsuk Kim;Youngmin Ku;Jung-Hwan Choi;Sunghoon Chun;Jonggyu Park","doi":"10.1109/TSIPI.2023.3235310","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3235310","url":null,"abstract":"In this article, we first propose and demonstrate a novel target-impedance (Z) extraction based optimal power distribution network (PDN) design methodology for high performance solid-state-drive (SSD) products. Instead of using the current profile of a chip power models (CPMs), the suggested methodology uses both measured current spectra and hierarchical PDN-Z models for target-Z calculation. We successfully measured the PCB-level current consumed by a memory package on SSD device using a test interposer specifically designed for current probing without interrupting the normal operations. Then, the measured PCB-level current is converted to the chip-level current value using Y-matrix of the hierarchical PDN-Z model. Compared with the simulation time for extracting a CPM current model, the proposed current measurement has relatively no time limit and, therefore, the target-Z covering a broadband frequency range is calculated based on the measured current spectrum. In addition, passive components such as decoupling capacitor are effectively selected using the deep-Q learning algorithm to satisfy the target- Z extracted by the proposed method and to optimize the PDN design. Finally, we verified for the first time that the mass-produced SSD product with the optimized PDN design satisfies the target voltage ripple in both simulation and measurement demonstrations.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"1-12"},"PeriodicalIF":0.0,"publicationDate":"2023-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

2022 Index IEEE Transactions on Signal and Power Integrity Vol. 1 2022年索引IEEE信号和功率完整性汇刊第1卷

IEEE Transactions on Signal and Power Integrity Pub Date : 2022-12-28 DOI: 10.1109/TSIPI.2022.3232196

引用次数: 0

IEEE Electromagnetic Compatibility Society Information IEEE电磁兼容性协会信息

IEEE Transactions on Signal and Power Integrity Pub Date : 2022-12-20 DOI: 10.1109/TSIPI.2022.3229779

引用次数: 0

IEEE Transactions on Signal and Power Integrity Information for Authors IEEE作者信号和功率完整性信息汇刊

IEEE Transactions on Signal and Power Integrity Pub Date : 2022-12-19 DOI: 10.1109/TSIPI.2022.3229735

引用次数: 0