IEEE transactions on biomedical circuits and systems最新文献_第3页

A Multi-Band Low-Supply-Voltage 16-QAM Transmitter Based on a Digital Fractional-N PLL With TDC Calibration for Capsule Endoscopy 基于数字分数n锁相环TDC校准的胶囊内窥镜多频带低供电电压16-QAM发射机。

IF 4.9

IEEE transactions on biomedical circuits and systems Pub Date : 2026-08-01 Epub Date: 2026-02-16 DOI: 10.1109/TBCAS.2026.3665262

Daehyeon Kwon;Donghyun Youn;Sohmyung Ha;Minkyu Je

{"title":"A Multi-Band Low-Supply-Voltage 16-QAM Transmitter Based on a Digital Fractional-N PLL With TDC Calibration for Capsule Endoscopy","authors":"Daehyeon Kwon;Donghyun Youn;Sohmyung Ha;Minkyu Je","doi":"10.1109/TBCAS.2026.3665262","DOIUrl":"10.1109/TBCAS.2026.3665262","url":null,"abstract":"This paper presents a highly digital transmitter capable of multi-band 16-QAM modulation for capsule endoscopy, which requires a high data rate with high energy efficiency and relatively high output power to meet receiver sensitivity specifications. A counter-assisted digital phase-locked loop (CDPLL) is utilized for generating clocks across multiple bands with low noise, resulting in good error vector magnitude (EVM) performance. The EVM generated by the CDPLL is less than 1% by using the proposed time-to-digital converter (TDC) calibration. A digital power amplifier with high power efficiency helps reduce the power consumption of the entire endoscopy capsule system, powered by a battery with limited capacity. Fabricated in a 180-nm CMOS process, the transmitter achieves a maximum data rate of 40 Mbps using 16-QAM modulation. At a 1.1-V supply, it achieves a 0.27/0.26-nJ/bit efficiency with a data rate of 40 Mbps, and the measured EVM is 3.24/3.7% while delivering a <inline-formula><tex-math>$boldsymbol{-}$</tex-math></inline-formula>5-dBm output power within a 10-MHz narrow bandwidth at 435/415 MHz for the wireless medical capsule endoscopy band in Europe and the biomedical band in China, respectively. The corresponding figure of merit is 0.86/0.82 nJ/(bit<inline-formula><tex-math>$cdot$</tex-math></inline-formula>mW) in each band.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"20 4","pages":"603-619"},"PeriodicalIF":4.9,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146208270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Guest Editorial—Special Section on Selected Papers From IEEE BioCAS 2025 嘉宾社论- IEEE BioCAS 2025论文精选专题

IF 4.9

IEEE transactions on biomedical circuits and systems Pub Date : 2026-08-01 Epub Date: 2026-07-29 DOI: 10.1109/TBCAS.2026.3713818

Andrea Cossettini;Chutham Sawigun;S. Abdollah Mirbozorgi

引用次数: 0

SPIRE: A 28nm Memory-Efficient Multi-Reservoir LSM Accelerator for Adaptive and Flexible Time-Series Classification SPIRE：一种用于自适应和灵活时间序列分类的28nm内存高效多库LSM加速器。

IF 4.9

IEEE transactions on biomedical circuits and systems Pub Date : 2026-08-01 Epub Date: 2026-02-25 DOI: 10.1109/TBCAS.2026.3668521

Darío Fernández-Khatiboun;Simon Richter;Yasser Rezaeiyan;Maryam Sadeghi;Corentin Piozin;Farshad Moradi

{"title":"SPIRE: A 28nm Memory-Efficient Multi-Reservoir LSM Accelerator for Adaptive and Flexible Time-Series Classification","authors":"Darío Fernández-Khatiboun;Simon Richter;Yasser Rezaeiyan;Maryam Sadeghi;Corentin Piozin;Farshad Moradi","doi":"10.1109/TBCAS.2026.3668521","DOIUrl":"10.1109/TBCAS.2026.3668521","url":null,"abstract":"Spiking Neural Networks are widely studied for their brain-inspired ability to process sequential information, yet their memory limitations often hinder the extraction of long-term dependencies. Reservoir computing, and in particular liquid state machines (LSM), has gained attention within this context for its ability to separate the recurrence and classification components into a recurrent reservoir liquid followed by a feedforward layer. However, existing LSM hardware suffers from significant design trade-offs, including large memory demands or performance degradation due to restrictive connectivity and weight precision. Inspired by these findings, we introduce SPIRE, a compact 1.13mm2 core area, fully digital multi-reservoir LSM with online learning adaptation. Implemented in TSMC 28nm CMOS technology, SPIRE is a memory-efficient multi-reservoir LSM tailored for time-series classification and edge deployment. By organizing up to eight reservoir ensembles into four parallelized cores, SPIRE enhances synaptic density and computational efficiency. Furthermore, SPIRE leverages on-the-fly generation of reservoir weights, reducing even further the memory footprint while supporting both sequential and parallelized dual operation modes. Benchmark results demonstrate that these design choices improve SPIRE’s synaptic density by up to 18.46<inline-formula><tex-math>$times$</tex-math></inline-formula> over prior works. SPIRE achieves 3.56 GSOPs/mm2 with just 4.91 pJ/SOP in sequential inference and up to 76.05 GSOPs/mm2 with 0.1 pJ/SOP in parallel configurations running at 55 MHz and 0.55 V.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"20 4","pages":"620-636"},"PeriodicalIF":4.9,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147292142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A 23-µJ-per-Frame All-on-Chip TinyML U-Net Processor for Real-Time Autonomous Image Segmentation in Miniaturized Ultrasound Devices 用于微型超声设备实时自主图像分割的23µj /帧全片TinyML U-Net处理器。

IF 4.9

IEEE transactions on biomedical circuits and systems Pub Date : 2026-08-01 Epub Date: 2026-03-23 DOI: 10.1109/TBCAS.2026.3676752

Zhiye Song;Ulkuhan Guler;Anantha Chandrakasan

{"title":"A 23-µJ-per-Frame All-on-Chip TinyML U-Net Processor for Real-Time Autonomous Image Segmentation in Miniaturized Ultrasound Devices","authors":"Zhiye Song;Ulkuhan Guler;Anantha Chandrakasan","doi":"10.1109/TBCAS.2026.3676752","DOIUrl":"10.1109/TBCAS.2026.3676752","url":null,"abstract":"Autonomous medical image segmentation enables critical applications, including urinary retention monitoring, prenatal fetal biometry, neuromodulation, and cardiovascular monitoring. Its deployment in wearable ultrasound patches demands on-device processing to preserve patient privacy and enable operation beyond clinical facilities. U-Net achieves state-of-the-art performance for biomedical segmentation, and recent binarized U-Nets retain high clinical accuracy with dramatically reduced computational cost. However, existing binary neural network (BNN) accelerators cannot support medical-grade segmentation due to missing accuracy-enhancing features, poor hardware utilization for compute-optimal layers, and memory bottlenecks requiring costly external DRAM. This work presents a 0.81 mm2 fully-integrated U-Net processor in 28nm featuring: 1) mixed-precision datapaths combining binary convolution with 4-bit skip connections for clinical accuracy; 2) systematic design space exploration across 9,390 configurations optimizing energy-latency tradeoffs; 3) interleaved memory representation and halo reuse for energy-efficient battery-powered operation; and 4) hardware-supported layer fusion and lossless compression eliminating external memory while reducing peak on-chip usage by 3.16x and 1.38x, respectively. Validated on bladder and fetal head segmentation datasets, the processor achieves 13.4 frames per second (fps) and 23 µJ per frame, enabling real-time autonomous monitoring in wearable medical devices.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"20 4","pages":"540-550"},"PeriodicalIF":4.9,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147505983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Characterization of a Pixel-Level Binarized Autocorrelator for Large Array Multispeckle Diffuse Correlation Spectroscopy under Photon-Starved Conditions 光子匮乏条件下用于大阵列多散斑漫射相关光谱的像素级二值化自相关器的表征。

IF 4.9

IEEE transactions on biomedical circuits and systems Pub Date : 2026-08-01 Epub Date: 2026-03-06 DOI: 10.1109/TBCAS.2026.3690899

Yining Wang;Yiyang Liu;Alistair Gorman;Robert K. Henderson

引用次数: 0

Ingestible Sensing Capsule with Magnetic-Based Localization Using a Wearable Belt. 使用可穿戴带进行磁定位的可摄入传感胶囊。

IF 4.9

IEEE transactions on biomedical circuits and systems Pub Date : 2026-07-31 DOI: 10.1109/TBCAS.2026.3719125

Ivan D Castro Miller, Vasileios Adamopoulos, Ramzy Rammouz, Ria Sijabat, Benjamin Calme, Tom Torfs

{"title":"Ingestible Sensing Capsule with Magnetic-Based Localization Using a Wearable Belt.","authors":"Ivan D Castro Miller, Vasileios Adamopoulos, Ramzy Rammouz, Ria Sijabat, Benjamin Calme, Tom Torfs","doi":"10.1109/TBCAS.2026.3719125","DOIUrl":"10.1109/TBCAS.2026.3719125","url":null,"abstract":"Wireless ingestible sensing capsules are of high relevance in the medical field due to their capability to measure biochemical parameters along the gastrointestinal (GI) tract and the potential to associate these with health-related conditions. Obtained sensor information is much more valuable when accompanied by accurate localization, since propagation speed can vary widely. However, most capsule localization systems presented in literature are either not accurate enough or imply bulky external units difficult to wear during daily life activities. Here, a novel ingestible sensing capsule 'GISMO-LOC' for pH and oxidation reduction potential sensing is presented. It features magnetic localization functionality enabled by a wearable transmitter belt. An in-vitro evaluation of the biochemical sensors confirmed the expected biochemical sensing functionality of the capsule. Evaluations of the location estimation in controlled conditions resulted in a mean absolute error (MAE) of 5.7 mm in the volume of interest. A GI trajectory reconstruction using a robot is also presented, with a MAE of 3.8 mm. An on-human evaluation during typical daily life activities resulted in most absolute errors below 2 cm for 'light' activities, 3 cm for 'moderate' activities and 4 cm for high-motion activities such as running. An evaluation of the belt comfort showed volunteer willingness to wear the belt during one week in daytime, while improvement aspects were identified to enable its use during the night. Finally, a limited in-vivo validation of the localization in an animal model was successfully performed. GISMO-LOC is therefore presented as a novel tool for GI tract related research.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":4.9,"publicationDate":"2026-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148649862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A 128-Channel Level-Crossing-Based Neural Digitization and Spike Sorting SoC With Compact Spatiotemporal Feature Extraction. 一种基于128通道交叉电平的神经数字化与脉冲分选SoC及紧凑的时空特征提取。

IF 4.9

IEEE transactions on biomedical circuits and systems Pub Date : 2026-07-16 DOI: 10.1109/TBCAS.2026.3714087

Yunzhu Chen, Xiaonan Xing, Xiaolin Yang, Yoontae Jung, Bernardo Tacca, Marian Verhelst, Georges Gielen, Carolina Mora Lopez

{"title":"A 128-Channel Level-Crossing-Based Neural Digitization and Spike Sorting SoC With Compact Spatiotemporal Feature Extraction.","authors":"Yunzhu Chen, Xiaonan Xing, Xiaolin Yang, Yoontae Jung, Bernardo Tacca, Marian Verhelst, Georges Gielen, Carolina Mora Lopez","doi":"10.1109/TBCAS.2026.3714087","DOIUrl":"10.1109/TBCAS.2026.3714087","url":null,"abstract":"High-density neural interfaces require power-efficient acquisition and on-chip processing for low-latency closed-loop operation. While level-crossing ADCs (LC-ADCs) offer efficient front-end acquisition, their integration with large-scale on-chip spike-sorting remains unexplored. In addition, existing on-chip spike sorters rely on temporal or spatial features alone, or on high-dimensional snippets, limiting the accuracy and efficiency. To address these limitations, this work presents a 128-channel neural digitization and spike-sorting system-on-chip (SoC) in 22-nm FDSOI CMOS, introducing three main novelties. First, a synchronized LC-ADC front-end coupled with pulse-domain spike detection reduces the detection power and area by 15.34% and 37.96% compared to NEO-based approaches with negligible accuracy loss. Second, a spatial spike realignment module corrects noise-induced electrode misalignment, improving the accuracy by 6.83%. Third, a compact spatiotemporal feature extractor uses 8 features to improve the accuracy by up to 9.18% while reducing the hardware cost. The chip consumes 1.2 µW and 0.00176 mm2 per channel for recording, and 1.09 µW and 0.0016 mm2 per channel for on-chip spike sorting. These results demonstrate the first large-scale co-integration of a synchronized LC-ADC front-end with hardware-efficient spatiotemporal spike sorting, enabling scalable and low-power neural interfaces.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":4.9,"publicationDate":"2026-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148474890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Edge On-Chip-Learning Convolutional Spiking Neural Network Processor Based on Error Backpropagation via Spatiotemporal Nodes of Spike Events. 基于脉冲事件时空节点误差反向传播的边缘片上学习卷积脉冲神经网络处理器。

IF 4.9

IEEE transactions on biomedical circuits and systems Pub Date : 2026-07-07 DOI: 10.1109/TBCAS.2026.3711044

Haibing Wang, Zhengqing Zhong, Liang Liang, Ying Jiang, Yingcheng Lin, Liyuan Liu, Cong Shi

{"title":"An Edge On-Chip-Learning Convolutional Spiking Neural Network Processor Based on Error Backpropagation via Spatiotemporal Nodes of Spike Events.","authors":"Haibing Wang, Zhengqing Zhong, Liang Liang, Ying Jiang, Yingcheng Lin, Liyuan Liu, Cong Shi","doi":"10.1109/TBCAS.2026.3711044","DOIUrl":"10.1109/TBCAS.2026.3711044","url":null,"abstract":"While Spiking Neural Networks (SNNs) offer high energy efficiency for edge computing, implementing on-chip backpropagation for convolutional topologies remains challenging due to substantial memory and logic overhead. Existing hardware mostly relies on offline training or local heuristic rules, which limits feature extraction in complex tasks. This paper presents a convolutional SNN processor featuring ConvTempo, an end-to-end global optimization framework. By restricting each neuron to fire at most once, the algorithm executes surrogate-gradient backpropagation sparsely at maximum membrane potential nodes, minimizing gradient computation. Simultaneously, a dedicated Output Channel- First (OC-First) scheduling mechanism reduces the membrane-potential-related intermediate state storage to O(N), while the Time-Channel Indexed cache reduces the AER storage overhead through compact spike-event encoding. Prototyped on a Xilinx Zynq-7045 FPGA at 100 MHz, the processor utilizes merely 8 DSPs alongside 94.5 Block RAMs (BRAMs) while consuming 0.589 W. Compared with an STDP-based baseline using the same lightweight convolutional topology, this work achieves absolute accuracy improvements of 0.64%, 1.29%, and 2.69% on MNIST, Fashion-MNIST, and ETH-80, respectively. Despite the implementation of chain-rule-based global surrogate-gradient backpropagation, the logic resource utilization remains competitive with lightweight shallow-topology designs, providing a high-accuracy on-chip learning solution for resource-constrained edge applications.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":4.9,"publicationDate":"2026-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148407479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ANP-R: A 22nm 0.88pJ/SOP Asynchronous SNN-based Processor with Coarse-Grained Reconfigurable Architecture Enabling Multisensory On-chip Incremental Learning for Edge AI. ANP-R：基于22nm 0.88pJ/SOP的粗粒度可重构异步snn处理器，支持边缘人工智能的多感官片上增量学习。

IF 4.9

IEEE transactions on biomedical circuits and systems Pub Date : 2026-06-29 DOI: 10.1109/TBCAS.2026.3708212

Ziyi Cheng, Dexuan Huo, Jilin Zhang, Zhihua Wang, Hong Chen

{"title":"ANP-R: A 22nm 0.88pJ/SOP Asynchronous SNN-based Processor with Coarse-Grained Reconfigurable Architecture Enabling Multisensory On-chip Incremental Learning for Edge AI.","authors":"Ziyi Cheng, Dexuan Huo, Jilin Zhang, Zhihua Wang, Hong Chen","doi":"10.1109/TBCAS.2026.3708212","DOIUrl":"10.1109/TBCAS.2026.3708212","url":null,"abstract":"Spiking Neural Networks (SNNs) have emerged as a promising paradigm for brain-inspired edge computing. Leveraging binary spikes and local learning rules, SNNs enable energy-efficient on-chip learning and rapid adaptation to changing environments, which is crucial for edge AI that needs to learn continuously from new data. However, many SNN processors enabling on-chip learning for edge computing confront a trade-off: small-scale task-specific designs offer low power but poor multi-task inference accuracy, while large-scale general-purpose designs achieve high multi-task accuracy at the cost of large memory and poor energy efficiency. To overcome this challenge, this paper presents ANP-R, a 22nm asynchronous SNN-based edge AI processor with coarse-grained reconfigurable architecture enabling one-shot, few-shot, batch and incremental on-chip learning. The processor integrates 64 cores containing 4096 neurons and 0.262 million synapses. Two key features are proposed: 1) An asynchronous coarse-grained reconfigurable architecture that supports various STDP-based SNN topologies. These topologies enable over 95% average accuracy across four sensory tasks; 2) an energy-efficient asynchronous training method incorporating a self-adaptive synaptic weight update mechanism reducing up to 65% redundant updates without accuracy loss, and a trained weights low-bit width coding method reducing up to 50% storage cost with 0.3% accuracy loss. Measurement results demonstrate 92.1% accuracy for hand gesture classification, 93.9% for keyword spotting, 98.6% for object recognition and 99.2% for gas identification. Compared with state-of-the-art SNN-based chips, this work achieves up to 6.02x, 8.61x and 7.1% improvement in energy efficiency, energy per step, and accuracy, respectively.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":4.9,"publicationDate":"2026-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148355095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A VPG-Based Adaptive Windowing PPG Sensor IC for Low-Power Wearable Monitoring. 低功耗可穿戴监测中基于vpg的自适应加窗PPG传感器集成电路。

IF 4.9

IEEE transactions on biomedical circuits and systems Pub Date : 2026-06-29 DOI: 10.1109/TBCAS.2026.3707974

Kyu-Jin Choi, ByungJun Kim, Jae-Yoon Sim

{"title":"A VPG-Based Adaptive Windowing PPG Sensor IC for Low-Power Wearable Monitoring.","authors":"Kyu-Jin Choi, ByungJun Kim, Jae-Yoon Sim","doi":"10.1109/TBCAS.2026.3707974","DOIUrl":"https://doi.org/10.1109/TBCAS.2026.3707974","url":null,"abstract":"This paper presents an energy-efficient photoplethysmography (PPG) sensor IC with adaptive windowing for low-power wearable monitoring. By utilizing the first derivative of the PPG signal (i.e., the velocity of PPG, VPG), the proposed algorithm tracks the PPG peaks and valleys (PAVs), enabling higher sampling rates only when necessary. Validated on the BIDMC dataset, the proposed VPG-based method reduces the PAV missing rate from 9.90% to 3.81% compared with the period-based algorithm. Additional BIDMC evaluations under additive noise and periodic artifact injection characterize its operating boundary, while representative walking examples from the PTT dataset illustrate PAV tracking under real motion-degraded conditions. The proposed IC, fabricated in a 180-nm CMOS process, is validated through in vivo measurements against a clinical-grade reference device. The system achieves mean absolute errors (MAEs) of 0.73 bpm for heart rate and 0.53% for SpO2, while reducing the total power consumption to 10.42 μW per channel, corresponding to a 53% reduction. These results demonstrate a practical low-power PPG sensing solution for wearable monitoring.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":4.9,"publicationDate":"2026-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148355084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0