IEEE transactions on biomedical circuits and systems最新文献

{"title":"Reducing False Alarms in Wearable Seizure Detection With EEGformer: A Compact Transformer Model for MCUs","authors":"Paola Busia;Andrea Cossettini;Thorir Mar Ingolfsson;Simone Benatti;Alessio Burrello;Victor J. B. Jung;Moritz Scherer;Matteo A. Scrugli;Adriano Bernini;Pauline Ducouret;Philippe Ryvlin;Paolo Meloni;Luca Benini","doi":"10.1109/TBCAS.2024.3357509","DOIUrl":"10.1109/TBCAS.2024.3357509","url":null,"abstract":"The long-term, continuous analysis of electroencephalography (EEG) signals on wearable devices to automatically detect seizures in epileptic patients is a high-potential application field for deep neural networks, and specifically for transformers, which are highly suited for end-to-end time series processing without handcrafted feature extraction. In this work, we propose a small-scale transformer detector, the EEGformer, compatible with unobtrusive acquisition setups that use only the temporal channels. EEGformer is the result of a hardware-oriented design exploration, aiming for efficient execution on tiny low-power micro-controller units (MCUs) and low latency and false alarm rate to increase patient and caregiver acceptance.Tests conducted on the CHB-MIT dataset show a 20% reduction of the onset detection latency with respect to the state-of-the-art model for temporal acquisition, with a competitive 73% seizure detection probability and 0.15 false-positive-per-hour (FP/h). Further investigations on a novel and challenging scalp EEG dataset result in the successful detection of 88% of the annotated seizure events, with 0.45 FP/h.We evaluate the deployment of the EEGformer on three commercial low-power computing platforms: the single-core Apollo4 MCU and the GAP8 and GAP9 parallel MCUs. The most efficient implementation (on GAP9) results in as low as 13.7 ms and 0.31 mJ per inference, demonstrating the feasibility of deploying the EEGformer on wearable seizure detection systems with reduced channel count and multi-day battery duration.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10412626","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139541540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Wearable Real-Time System for Simultaneous Wireless Power and Data Transmission to Cortical Visual Prosthesis","authors":"Gian Luca Barbruni;Francesca Rodino;Paolo Motto Ros;Danilo Demarchi;Diego Ghezzi;Sandro Carrara","doi":"10.1109/TBCAS.2024.3357626","DOIUrl":"10.1109/TBCAS.2024.3357626","url":null,"abstract":"Wireless, miniaturised and distributed neural interfaces are emerging neurotechnologies. Although extensive research efforts contribute to their technological advancement, the need for real-time systems enabling simultaneous wireless information and power transfer toward distributed neural implants remains crucial. Here we present a complete wearable system including a software for real-time image capturing, processing and digital data transfer; an hardware for high radiofrequency generation and modulation via amplitude shift keying; and a 3-coil inductive link adapt to operate with multiple miniaturised receivers. The system operates in real-time with a maximum frame rate of 20 Hz, reconstructing each frame with a matrix of 32 × 32 pixels. The device generates a carrier frequency of 433.92 MHz. It transmits the highest power of 32 dBm with a data rate of 6 Mbps and a variable modulation index as low as 8\u0000<inline-formula><tex-math>$%$</tex-math></inline-formula>\u0000, thus potentially enabling wireless communication with 1024 miniaturised and distributed intracortical microstimulators. The system is primarily conceived as an external wearable device for distributed cortical visual prosthesis covering a visual field of 20\u0000<inline-formula><tex-math>$^{circ }$</tex-math></inline-formula>\u0000. At the same time, it is modular and versatile, being suitable for multiple applications requiring simultaneous wireless information and power transfer to large-scale neural interfaces.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139543862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"NeuroBus - Architecture for an Ultra-Flexible Neural Interface","authors":"Markus Sporer;Ioana-Georgiana Vasilaş;Ahmed Adžemović;Nicolas Graber;Stefan Reich;Calogero Gueli;Max Eickenscheidt;Ilka Diester;Thomas Stieglitz;Maurits Ortmanns","doi":"10.1109/TBCAS.2024.3354785","DOIUrl":"10.1109/TBCAS.2024.3354785","url":null,"abstract":"This article presents the system architecture for an implant concept called \u0000<italic>NeuroBus</i>\u0000. Tiny distributed direct digitizing neural recorder ASICs on an ultra-flexible polyimide substrate are connected in a bus-like structure, allowing short connections between electrode and recording front-end with low wiring effort and high customizability. The small size (344\u0000<inline-formula><tex-math>$,mu$</tex-math></inline-formula>\u0000m × 294 \u0000<inline-formula><tex-math>$mu$</tex-math></inline-formula>\u0000m) of the ASICs and the ultraflexible substrate allow a low bending stiffness, enabling the implant to adapt to the curvature of the brain and achieving high structural biocompatibility. We introduce the architecture, the integrated building blocks, and the post-CMOS processes required to realize a \u0000<italic>NeuroBus</i>\u0000, and we characterize the prototyped direct digitizing neural recorder front-end as well as polyimide-based ECoG brain interface. A rodent animal model is further used to validate the joint capability of the recording front-end and thin-film electrode array.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10400847","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139472907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Fast FPGA Hardware Accelerator for Remote Heart Rate Detection Based on RGB Vision","authors":"Jen-Yi Hsu;Ting-Yin Jiang;Paul C.-P. Chao","doi":"10.1109/TBCAS.2024.3354505","DOIUrl":"10.1109/TBCAS.2024.3354505","url":null,"abstract":"A fast hardware accelerator is created by this work via field programmable gate array (FPGA) to estimate heart rate (HR) through the video recorded by a RGB camera based on the technology of remote photoplethysmography (rPPG). The method of rPPG acquires physiological signals of a human body by analyzing the subtle color changes on the surface of the human skin. The hardware implementation of rPPG to estimate HR is proposed herein to aim for a much faster calculation speed than software for a number of applications, like heart failure pre-warning of an in-action athlete and drowsiness detection of a driver. In this accelerator, ICA (Independent Component Analysis) is used to recover the blood volume pulse from the raw signals of remote PPG, and then obtain the heart rate value. The architecture of the hardware circuit is described in Verilog HDL and verified by Quartus II, and also implemented in an Altera DE10-Standard FPGA board, which consists of image capture, heart rate algorithm and image display. A TRDB-D5M camera is utilized for image capture. Two experiments were conducted with image collecting duration of 16 seconds and 8 seconds respectively, and the commercial device Omron HEM-6111 was used as the golden value. The proposed system achieves an accuracy in (ME ± 1.96SD) of −0.76 ± 5.09 and −0.70 ± 8.71 bpm in the short periods of 16-second and 8-second versions, respectively, which outperforms all the reported prior works in combined computation time and accuracy.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139472810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of CMOS Analog Front-End Local-Field Potential Chopper Amplifier With Stimulation Artifact Tolerance for Real-Time Closed-Loop Deep Brain Stimulation SoC Applications","authors":"Chung-Yu Wu;Chi-Wei Huang;Yu-Wei Chen;Chin-Kai Lai;Chung-Chih Hung;Ming-Dou Ker","doi":"10.1109/TBCAS.2024.3352414","DOIUrl":"10.1109/TBCAS.2024.3352414","url":null,"abstract":"A CMOS analog front-end (AFE) local-field potential (LFP) chopper amplifier with stimulation artifact tolerance, improved right-leg driven (RLD) circuit, and improved auxiliary path is proposed. In the proposed CMOS AFE LFP chopper amplifier, common-mode artifact voltage (CMAV) and differential-mode artifact voltage (DMAV) removal using the analog template removal method are proposed to achieve good signal linearity during stimulation. An improved auxiliary path is employed to boost the input impedance and allow the negative stimulation artifact voltage passing through. The common-mode noise is suppressed by the improved RLD circuit. The chip is implemented in 0.18-\u0000<inline-formula><tex-math>${{bf mu m}}$</tex-math></inline-formula>\u0000 CMOS technology and the total chip area is 5.46-mm\u0000²\u0000. With the improved auxiliary path, the measured input impedance is larger than 133 M\u0000<inline-formula><tex-math>${bm{Omega}}$</tex-math></inline-formula>\u0000 in the signal bandwidth and reaches 8.2 G\u0000<inline-formula><tex-math>${bm{Omega}}$</tex-math></inline-formula>\u0000 at DC. With the improved RLD circuit, the measured CMRR is 131 – 144 dB in the signal bandwidth. Under 60-μs pulse width and 130-Hz constant current stimulation (CCS) with ±1-V CMAV and ±50-mV DMAV, the measured THD at the SC Amp output of fabricated AFE LFP chopper amplifier is 1.28%. The measurement results of In vitro agar tests have shown that with ±1.6-mA CCS pulses injecting to agar, the measured THD is 1.69%. Experimental results of both electrical and agar tests have verified that the proposed AFE LFP chopper amplifier has good stimulation artifact tolerance. The proposed CMOS AFE LFP chopper amplifier with analog template removal method is suitable for real-time closed-loop deep drain stimulation (DBS) SoC applications.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139418845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Bionic Localization Memristive Circuit Based on Spatial Cognitive Mechanisms of Hippocampus and Entorhinal Cortex","authors":"Zihui Tang;Xiaoping Wang;Chao Yang;Zhanfei Chen;Zhigang Zeng","doi":"10.1109/TBCAS.2024.3350135","DOIUrl":"10.1109/TBCAS.2024.3350135","url":null,"abstract":"In this article, a bionic localization memristive circuit is proposed, which mainly consists of head direction cell module, grid cell module, place cell module and decoding module. This work modifies the two-dimensional Continuous Attractor Network (CAN) model of grid cells into two one-dimensional models in X and Y directions. The head direction cell module utilizes memristors to integrate angular velocity and represents the real orientation of an agent. The grid cell module uses memristors to sense linear velocity and orientation signals, which are both self-motion cues, and encodes the position in space by firing in a periodic mode. The place cell module receives the grid cell module's output and fires in a specific position. The decoding module decodes the angle or place information and transfers the neuron state to a ‘one-hot’ code. This proposed circuit completes the localizing task in space and realizes in-memory computing due to the use of memristors, which can shorten the execution time. The functions mentioned above are implemented in LTSPICE. The simulation results show that the proposed circuit can realize path integration and localization. Moreover, it is shown that the proposed circuit has good robustness and low area overhead. This work provides a possible application idea in a prospective robot platform to help the robot localize and build maps.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139946618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Population-Specific Glucose Prediction in Diabetes Care With Transformer-Based Deep Learning on the Edge","authors":"Taiyu Zhu;Lei Kuang;Chengzhe Piao;Junming Zeng;Kezhi Li;Pantelis Georgiou","doi":"10.1109/TBCAS.2023.3348844","DOIUrl":"10.1109/TBCAS.2023.3348844","url":null,"abstract":"Leveraging continuous glucose monitoring (CGM) systems, real-time blood glucose (BG) forecasting is essential for proactive interventions, playing a crucial role in enhancing the management of type 1 diabetes (T1D) and type 2 diabetes (T2D). However, developing a model generalized to a population and subsequently embedding it within a microchip of a wearable device presents significant technical challenges. Furthermore, the domain of BG prediction in T2D remains under-explored in the literature. In light of this, we propose a population-specific BG prediction model, leveraging the capabilities of the temporal fusion Transformer (TFT) to adjust predictions based on personal demographic data. Then the trained model is embedded within a system-on-chip, integral to our low-power and low-cost customized wearable device. This device seamlessly communicates with CGM systems through Bluetooth and provides timely BG predictions using edge computing. When evaluated on two publicly available clinical datasets with a total of 124 participants with T1D or T2D, the embedded TFT model consistently demonstrated superior performance, achieving the lowest prediction errors when compared with a range of machine learning baseline methods. Executing the TFT model on our wearable device requires minimal memory and power consumption, enabling continuous decision support for more than 51 days on a single Li-Poly battery charge. These findings demonstrate the significant potential of the proposed TFT model and wearable device in enhancing the quality of life for people with diabetes and effectively addressing real-world challenges.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139076429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"GEMA: A Genome Exact Mapping Accelerator Based on Learned Indexes","authors":"Mohaddeseh Sharei;Mehdi Kamal;Ali Afzali-Kusha;Massoud Pedram","doi":"10.1109/TBCAS.2023.3348152","DOIUrl":"10.1109/TBCAS.2023.3348152","url":null,"abstract":"In this article, we introduce GEMA, a genome exact mapping accelerator based on learned indexes, specifically designed for FPGA implementation. GEMA utilizes a machine learning (ML) algorithm to precisely locate the exact position of read sequences within the original sequence. To enhance the accuracy of the trained ML model, we incorporate data augmentation and data-distribution-aware partitioning techniques. Additionally, we present an efficient yet low-overhead error recovery technique. To map long reads more efficiently, we propose a speculative prefetching approach, which reduces the required memory bandwidth. Furthermore, we suggest an FPGA-based architecture for implementing the proposed mapping accelerator, optimizing the accesses to off-chip memory. Our studies demonstrate that GEMA achieves up to 1.36 × higher speed for short reads compared to the corresponding results reported in recently published exact mapping accelerators. Moreover, GEMA achieves up to ∼22 × faster mapping of long reads compared to the available results for the longest mapped reads using these accelerators.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139076428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Brain Feature Extraction With an Artifact-Tolerant Multiplexed Time-Encoding Neural Frontend for True Real-Time Closed-Loop Neuromodulation","authors":"Marco Francesco Carlino;Georges Gielen","doi":"10.1109/TBCAS.2023.3344889","DOIUrl":"10.1109/TBCAS.2023.3344889","url":null,"abstract":"Closed-loop neuromodulation is emerging as a more effective and targeted solution for the treatment of neurological symptoms compared to traditional open-loop stimulation. The majority of the present designs lack the ability to continuously record brain activity during electrical stimulation; hence they cannot fully monitor the treatment's effectiveness. This is due to the large stimulation artifacts that can saturate the sensitive readout circuits. To overcome this challenge, this work presents a rapid-artifact-recovery time-multiplexed neural readout frontend in combination with backend linear interpolation to reconstruct the artifact-corrupted local field potentials' (LFP) features. Our hybrid technique is an alternative approach to avoid power-hungry large-dynamic-range readout architectures or large and complex artifact template subtraction circuits. We discuss the design and measurements of a prototype implementation of the proposed readout frontend in 180-nm CMOS. It combines time multiplexing and time-domain conversion in a novel 13-bit incremental ADC, requiring only 0.0018 mm\u0000²\u0000/channel of readout area despite the large 180-nm CMOS process used, while consuming only 4.51 \u0000<inline-formula><tex-math>$mu$</tex-math></inline-formula>\u0000W/channel. This is the smallest reported area for stimulation-voltage-compatible technologies (i.e. \u0000<inline-formula><tex-math>$ge$</tex-math></inline-formula>\u0000 65 nm). The frontend also yields a best-in-class peak total harmonic distortion of −72.6 dB @2.5-mVpp input, thanks to its implicit DAC mismatch-error shaping property. We employ the chip to measure brain LFP signals corrupted with artifacts, then perform linear interpolation and feature extraction on the measured signals and evaluate the reconstruction quality, using a set of sixteen commonly used features and three stimulation scenarios. The results show relative accuracies above 95% with respect to the situation without artifacts. This work is an ideal candidate for integration in high-channel-count true closed-loop neuromodulation systems.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138833709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Multi-Functional CMOS Biosensor Array With On-Chip DEP-Assisted Sensing for Rapid Low-Concentration Analyte Detection and Close-Loop Particle Manipulation With No External Electrodes","authors":"Dongwon Lee;Doohwan Jung;Fuze Jiang;Gregory Villiam Junek;Jongseok Park;Hangxing Liu;Ying Kong;Adam Wang;Youngin Kim;Kyung-Sik Choi;Jing Wang;Hua Wang","doi":"10.1109/TBCAS.2023.3343068","DOIUrl":"10.1109/TBCAS.2023.3343068","url":null,"abstract":"This article presents a fully-integrated dielectrophoresis (DEP)-assisted multi-functional CMOS biosensor array chip with 4096 working electrodes (WEs), 12288 photodiodes (PDs), reference electrodes (REs), and counter electrodes (CEs), while each WE and photodiode can be reconfigured to support on-chip DEP actuation, electrochemical potentiostat, optical shadow imaging, and complex impedance sensing. The proposed CMOS biosensor is an example of an actuation-assisted label-free biosensor for the rapid sensing of low-concentration analytes. The DEP actuator of the proposed CMOS biosensor does not require any external electrode. Instead, on-chip WE pairs can be re-used for DEP actuation to simplify the sensor array design. The CMOS biosensor is implemented in a standard 130-nm BiCMOS process. Theoretical analyses and finite element method (FEM) simulations of the on-chip DEP operations are conducted as proof of concept. Biological assay measurements (DEP actuation/electrochemical potentiostat/impedance sensing) with \u0000<italic>E.coli</i>\u0000 bacteria and microbeads (optical shadow imaging) demonstrate rapid detection of low-concentration analytes and simultaneous manipulation and detection of large particles. The on-chip DEP operations draw the analytes closer to the sensor electrode surface, which overcomes the diffusion limit and accelerates low-concentration analyte sensing. Moreover, the DEP-based movement of large particles can be readily detected by on-chip photodiode arrays to achieve close-loop manipulation and sensing of particles and droplets. These show the unique advantages of the DEP-assisted multi-functional biosensor.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138814440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}