IEEE transactions on biomedical circuits and systems最新文献

{"title":"MorphBungee: A 65-nm 7.2-mm2 27-µJ/Image Digital Edge Neuromorphic Chip With on-Chip 802-Frame/s Multi-Layer Spiking Neural Network Learning","authors":"Tengxiao Wang;Min Tian;Haibing Wang;Zhengqing Zhong;Junxian He;Fang Tang;Xichuan Zhou;Yingcheng Lin;Shuang-Ming Yu;Liyuan Liu;Cong Shi","doi":"10.1109/TBCAS.2024.3412908","DOIUrl":"10.1109/TBCAS.2024.3412908","url":null,"abstract":"This paper presents a digital edge neuromorphic spiking neural network (SNN) processor chip for a variety of edge intelligent cognitive applications. This processor allows high-speed, high-accuracy and fully on-chip spike-timing-based multi-layer SNN learning. It is characteristic of hierarchical multi-core architecture, event-driven processing paradigm, meta-crossbar for efficient spike communication, and hybrid and reconfigurable parallelism. A prototype chip occupying an active silicon area of 7.2 mm² was fabricated using a 65-nm 1P9M CMOS process. when running a 256-256-256-256-200 4-layer fully-connected SNN on downscaled 16 × 16 MNIST images. it typically achieved a high-speed throughput of 802 and 2270 frames/s for on-chip learning and inference, respectively, with a relatively low power dissipation of around 61 mW at a 100 MHz clock rate under a 1.0V core power supply, Our on-chip learning results in comparably high visual recognition accuracies of 96.06%, 83.38%, 84.53%, 99.22% and 100% on the MNIST, Fashion-MNIST, ETH-80, Yale-10 and ORL-10 datasets, respectively. In addition, we have successfully applied our neuromorphic chip to demonstrate high-resolution satellite cloud image segmentation and non-visual tasks including olfactory classification and textural news categorization. These results indicate that our neuromorphic chip is suitable for various intelligent edge systems under restricted cost, energy and latency budgets while requiring in-situ self-adaptative learning capability.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 1","pages":"209-225"},"PeriodicalIF":0.0,"publicationDate":"2024-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141307673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Real-Time Motor Unit Tracking From sEMG Signals With Adaptive ICA on a Parallel Ultra-Low Power Processor","authors":"Mattia Orlandi;Pierangelo Maria Rapa;Marcello Zanghieri;Sebastian Frey;Victor Kartsch;Luca Benini;Simone Benatti","doi":"10.1109/TBCAS.2024.3410840","DOIUrl":"10.1109/TBCAS.2024.3410840","url":null,"abstract":"Spike extraction by blind source separation (BSS) algorithms can successfully extract physiologically meaningful information from the sEMG signal, as they are able to identify motor unit (MU) discharges involved in muscle contractions. However, BSS approaches are currently restricted to isometric contractions, limiting their applicability in real-world scenarios. We present a strategy to track MUs across different dynamic hand gestures using adaptive independent component analysis (ICA): first, a pool of MUs is identified during isometric contractions, and the decomposition parameters are stored; during dynamic gestures, the decomposition parameters are updated online in an unsupervised fashion, yielding the refined MUs; then, a Pan-Tompkins-inspired algorithm detects the spikes in each MUs; finally, the identified spikes are fed to a classifier to recognize the gesture. We validate our approach on a 4-subject, 7-gesture + rest dataset collected with our custom 16-channel dry sEMG armband, achieving an average balanced accuracy of 85.58 \u0000<inline-formula><tex-math>$pm$</tex-math></inline-formula>\u0000 14.91% and macro-F1 score of 85.86 \u0000<inline-formula><tex-math>$pm$</tex-math></inline-formula>\u0000 14.48%. We deploy our solution onto GAP9, a parallel ultra-low-power microcontroller specialized for computation-intensive linear algebra applications at the edge, obtaining an energy consumption of 4.72 mJ @ 240 MHz and a latency of 121.3 ms for each 200 ms-long window of sEMG signal.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 4","pages":"771-782"},"PeriodicalIF":0.0,"publicationDate":"2024-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141289049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Adaptable Dual-Tuned Optically Controlled on-Coil RF Power Amplifier for MRI","authors":"Natalia Gudino","doi":"10.1109/TBCAS.2024.3403093","DOIUrl":"10.1109/TBCAS.2024.3403093","url":null,"abstract":"An adaptable optically controlled RF power amplifier (RFPA) is presented for direct implementation on the Magnetic Resonance Imaging (MRI) transmit coil. Operation at ¹H and multiple X-nuclei frequencies for 7T MRI was demonstrated through the automated tuning of an effective voltage-modulated inductor located in the gate driver circuit of the FET switches in the different amplification stages. Through this automated tuning, the amplifier can be adapted from the control to operate at the selected ¹H and X-nuclei frequency in a multinuclear MRI study. Bench and MRI data acquired with the adaptable dual-tuned on-coil RFPA is presented. This technology should allow a simpler, more efficient and versatile implementation of the multinuclear multichannel MRI hardware. Ultimately, to extend the research on MRI detectable nuclei that can provide new insights about healthy and diseased tissue.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 1","pages":"165-173"},"PeriodicalIF":0.0,"publicationDate":"2024-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141263580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Supervised Contrastive Learning Framework and Hardware Implementation of Learned ResNet for Real-Time Respiratory Sound Classification","authors":"Jinhai Hu;Cong Sheng Leow;Shuailin Tao;Wang Ling Goh;Yuan Gao","doi":"10.1109/TBCAS.2024.3409584","DOIUrl":"10.1109/TBCAS.2024.3409584","url":null,"abstract":"This paper presents a supervised contrastive learning (SCL) framework for respiratory sound classification and the hardware implementation of learned ResNet on field programmable gate array (FPGA) for real-time monitoring. At the algorithmic level, multiple techniques such as features augmentation and MixUp are combined holistically to mitigate the impact of data scarcity and imbalanced classes in the training dataset. Bayesian optimization further enhances the classification accuracy through parameter tuning in pre-processing and SCL. The proposed framework achieves 0.8725 total score (including runtime score) on a ResNet-18 model in both event and record multi-class classification tasks using the SJTU Paediatric Respiratory Sound Database (SPRSound). In addition, algorithm-hardware co-optimizations including Quantization-Aware Training (QAT), merge of network layers, optimization of memory size and number of parallel threads are performed for hardware implementation on FPGA. This approach reduces 40% model size and 70% computation latency. The learned ResNet is implemented on a Xilinx Zynq ZCU102 FPGA with 16ms latency and less than 2% inference score degradation compared to the software model.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 1","pages":"185-195"},"PeriodicalIF":0.0,"publicationDate":"2024-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141263563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 1.11 mm2 IVUS SoC With $pm 50^{circ}$-Range Plane Wave Transmit Beamforming at 40 MHz","authors":"Xitie Zhang;Evren F. Arkan;Coskun Tekes;M. Sait Kilinc;Tzu-Han Wang;F. Levent Degertekin;Shaolan Li","doi":"10.1109/TBCAS.2024.3409162","DOIUrl":"10.1109/TBCAS.2024.3409162","url":null,"abstract":"Intravascular ultrasound (IVUS) imaging catheters are significant tools for cardiovascular interventions, and their use can be expanded by realizing IVUS imaging guidewires and microcatheters. The miniaturization of these devices creates challenges in SNR due to the need for higher frequencies to provide adequate resolution. An integrated IVUS system with transmit beamforming can mitigate these limitations. This work presents the first practical highly integrated system-on-a-chip (SoC) with plane wave transmit beamforming at 40 MHz for IVUS on guidewire or microcatheters. The front-end circuitry has a 20-channel ultrasound transmitter (Tx) and receiver (Rx) array interfaced with a capacitive micromachined ultrasound transducer (CMUT) array. During each firing, all 20 Tx are excited with the same analog delay with respect to each other, which can be continuously adjusted between <inline-formula><tex-math>$sim$</tex-math></inline-formula>0 and 10 ns in two directions, generating a steerable plane wave in a range of +/-50<inline-formula><tex-math>${}^{circ}$</tex-math></inline-formula> for a phased array at 40 MHz. The unit delays are generated via a voltage-controlled delay line (VCDL), which only needs two external controls, one tuning the unit delay and the other determining the steering direction. The SoC is fabricated using a 180-nm high-voltage (HV) CMOS process and features a slender active area of 0.3 mm <inline-formula><tex-math>$times$</tex-math></inline-formula> 3.7 mm. The proposed SoC consumes 31.3 mW during the receiving mode. The beamformer's functionality and the SoC's overall performance were validated through acoustic characterization and imaging experiments.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 1","pages":"174-184"},"PeriodicalIF":0.0,"publicationDate":"2024-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141249075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Energy-Efficient Spectral Analysis of ECGs on Resource Constrained IoT Devices.","authors":"Charalampos Eleftheriadis, Georgios Karakonstantis","doi":"10.1109/TBCAS.2024.3406520","DOIUrl":"https://doi.org/10.1109/TBCAS.2024.3406520","url":null,"abstract":"<p><p>Power spectral analysis (PSA) is one of the most popular and insightful methods, currently employed in several biomedical applications, aiming to identify and monitor various health related conditions. Among the most common applications of PSA is heart rate variability (HRV) analysis, which allows the extraction of further insights compared with conventional time-domain methods. Unfortunately, existing PSA approaches exhibit high computational complexity, hindering their execution on power-constrained embedded internet of things (IoT) devices. Such IoT devices are increasingly used for monitoring various conditions mainly by processing the input signals in the less complex time-domain. In this paper, a new low-complexity PSA system based on fast Gaussian gridding (FGG) is proposed, which can be used to calculate the Lomb-Scargle periodogram (LSP) of a non-uniformly spaced RR tachogram. The proposed approach is implemented on a popular ARM Cortex-M4 based embedded system, which is widely used in common wearables, and compared with conventional LSP-based approaches. Utilizing this experimental setup, a meticulous analysis is performed in terms of power, performance and quality under different operational settings, such as the total input/output samples, precision of computations, computer arithmetic (floating/fixed-point), and clock frequency. The experimental results show that the proposed FGG-based LSP approach, when specifically optimized for the targeted embedded device, outperforms existing approaches by up-to 92.99% and 91.70% in terms of energy consumption and total execution time respectively, with minimal accuracy loss.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141177137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultra-Compact Pulse Charger for Lithium Polymer Battery with Simple Built-in Resistance Compensation in Biomedical Applications.","authors":"Yemin Kim, Junhyuck Lee, Byunghun Lee","doi":"10.1109/TBCAS.2024.3401846","DOIUrl":"https://doi.org/10.1109/TBCAS.2024.3401846","url":null,"abstract":"Active implantable medical devices (AIMDs) rely on batteries for uninterrupted operation and patient safety. Therefore, it is critical to ensure battery safety and longevity. To achieve this, constant current/constant voltage (CC/CV) methods have been commonly used and research has been conducted to compensate for the effects of built-in resistance (BIR) of batteries. However, conventional CC/CV methods may pose the risk of lithium plating. Furthermore, conventional compensation methods for BIR require external components, complex algorithms, or large chip sizes, which inhibit the miniaturization and integration of AIMDs. To address this issue, we have developed a pulse charger that utilizes pulse current to ensure battery safety and facilitate easy compensation for BIR. A comparison with previous research on BIR compensation shows that our approach achieves the smallest chip size of 0.0062 mm2 and the lowest system complexity using 1-bit ADC. In addition, we have demonstrated a reduction in charging time by at least 44.4% compared to conventional CC/CV methods, validating the effectiveness of our system's BIR compensation. The compact size and safety features of the proposed charging system make it promising for AIMDs, which have space-constrained environments.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"55 25","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140970496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"BrainFuseNet: Enhancing Wearable Seizure Detection Through EEG-PPG-Accelerometer Sensor Fusion and Efficient Edge Deployment","authors":"Thorir Mar Ingolfsson;Xiaying Wang;Upasana Chakraborty;Simone Benatti;Adriano Bernini;Pauline Ducouret;Philippe Ryvlin;Sándor Beniczky;Luca Benini;Andrea Cossettini","doi":"10.1109/TBCAS.2024.3395534","DOIUrl":"10.1109/TBCAS.2024.3395534","url":null,"abstract":"This paper introduces \u0000<sc>BrainFuseNet</small>\u0000, a novel lightweight seizure detection network based on the sensor fusion of electroencephalography (EEG) with photoplethysmography (PPG) and accelerometer (ACC) signals, tailored for low-channel count wearable systems. \u0000<sc>BrainFuseNet</small>\u0000 utilizes the Sensitivity-Specificity Weighted Cross-Entropy (SSWCE), an innovative loss function incorporating sensitivity and specificity, to address the challenge of heavily unbalanced datasets. The \u0000<sc>BrainFuseNet</small>\u0000-SSWCE approach successfully detects \u0000<inline-formula><tex-math>$93.5%$</tex-math></inline-formula>\u0000 seizure events on the CHB-MIT dataset (\u0000<inline-formula><tex-math>$76.34%$</tex-math></inline-formula>\u0000 sample-based sensitivity), for EEG-based classification with only four channels. On the PEDESITE dataset, we demonstrate a sample-based sensitivity and false positive rate of \u0000<inline-formula><tex-math>$60.66%$</tex-math></inline-formula>\u0000 and \u0000<inline-formula><tex-math>$1.18$</tex-math></inline-formula>\u0000 FP/h, respectively, when considering EEG data alone. Additionally, we demonstrate that integrating PPG signals increases the sensitivity to \u0000<inline-formula><tex-math>$61.22%$</tex-math></inline-formula>\u0000 (successfully detecting \u0000<inline-formula><tex-math>$92%$</tex-math></inline-formula>\u0000 seizure events) while decreasing the number of false positives to \u0000<inline-formula><tex-math>$1.0$</tex-math></inline-formula>\u0000 FP/h. Finally, when ACC data are also considered, the sensitivity increases to \u0000<inline-formula><tex-math>$64.28%$</tex-math></inline-formula>\u0000 (successfully detecting \u0000<inline-formula><tex-math>$95%$</tex-math></inline-formula>\u0000 seizure events) and the number of false positives drops to only \u0000<inline-formula><tex-math>$0.21$</tex-math></inline-formula>\u0000 FP/h for sample-based estimations, with less than one false alarm per day when considering event-based estimations. \u0000<sc>BrainFuseNet</small>\u0000 is resource-friendly and well-suited for implementation on low-power embedded platforms, and we evaluate its performance on GAP9, a state-of-the-art parallel ultra-low power (PULP) microcontroller for tiny Machine Learning applications on wearables. The implementation on GAP9 achieves an energy efficiency of \u0000<inline-formula><tex-math>$21.43$</tex-math></inline-formula>\u0000 GMAC/s/W, with an energy consumption per inference of only \u0000<inline-formula><tex-math>$0.11$</tex-math></inline-formula>\u0000 mJ at high performance (\u0000<inline-formula><tex-math>$412.54$</tex-math></inline-formula>\u0000 MMAC/s). The \u0000<sc>BrainFuseNet</small>\u0000-SSWCE method demonstrates effective and accurate seizure detection on heavily imbalanced datasets while achieving state-of-the-art performance in the false positive rate and being well-suited for deployment on energy-constrained edge devices.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 4","pages":"720-733"},"PeriodicalIF":0.0,"publicationDate":"2024-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10511055","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140827553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A CMOS BD-BCI: Neural Recorder With Two-Step Time-Domain Quantizer and Multipolar Stimulator With Dual-Mode Charge Balancing","authors":"Ahmad Reza Danesh;Haoran Pu;Mahyar Safiallah;An H. Do;Zoran Nenadic;Payam Heydari","doi":"10.1109/TBCAS.2024.3391190","DOIUrl":"10.1109/TBCAS.2024.3391190","url":null,"abstract":"This work presents a bi-directional brain-computer interface (BD-BCI) including a high-dynamic-range (HDR) two-step time-domain neural acquisition (TTNA) system and a high-voltage (HV) multipolar neural stimulation system incorporating dual-mode time-based charge balancing (DTCB) technique. The proposed TTNA includes four independent recording modules that can sense microvolt neural signals while tolerating large stimulation artifacts. In addition, it exhibits an integrated input-referred noise of 2.3 \u0000<inline-formula><tex-math>$mu$</tex-math></inline-formula>\u0000V\u0000_rms\u0000 from 0.1- to 250-Hz and can handle a linear input-signal swing of up to 340 mV\u0000_PP\u0000. The multipolar stimulator is composed of four standalone stimulators each with a maximum current of up to 14 mA (\u0000<inline-formula><tex-math>$pm$</tex-math></inline-formula>\u000020-V of voltage compliance) and 8-bit resolution. An inter-channel interference cancellation circuitry is introduced to preserve the accuracy and effectiveness of the DTCB method in the multipolar-stimulation configuration. Fabricated in an HV 180-nm CMOS technology, the BD-BCI chipset undergoes extensive \u0000<italic>in-vitro</i>\u0000 and \u0000<italic>in-vivo</i>\u0000 evaluations. The recording system achieves a measured SNDR, SFDR, and CMRR of 84.8 dB, 89.6 dB, and \u0000<inline-formula><tex-math>$&gt;$</tex-math></inline-formula>\u0000105 dB, respectively. The measurement results verify that the stimulation system is capable of performing high-precision charge balancing with \u0000<inline-formula><tex-math>$pm$</tex-math></inline-formula>\u00002 mV and \u0000<inline-formula><tex-math>$pm$</tex-math></inline-formula>\u00007.5 mV accuracy in the interpulse-bounded time-based charge balancing (TCB) and artifactless TCB modes, respectively.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 6","pages":"1354-1370"},"PeriodicalIF":0.0,"publicationDate":"2024-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10505036","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140630440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Direct-Digital 40 $mu$A 100 kb/s Intracardiac Communication Receiver With 250 $mu$s Startup Time for Low Duty-Cycle Leadless Pacemaker Synchronization","authors":"Adrian Ryser;Christof Baeriswyl;Michel Moser;Jürgen Burger;Tobias Reichlin;Thomas Niederhauser;Andreas Haeberlin","doi":"10.1109/TBCAS.2024.3390620","DOIUrl":"10.1109/TBCAS.2024.3390620","url":null,"abstract":"The first commercial dual-chamber leadless pacemaker (LLPM) was introduced recently. The system combines two separate implants situated in the right atrium and the right ventricle of the heart. Implant synchronization is accomplished with conductive intracardiac communication (CIC) using the myocardium and blood as transmission channel. Successful implant synchronization of this dual-chamber LLPM has been demonstrated. However, the continuously active synchronization transceivers, consuming about 800 nA, cause a 25-45\u0000<inline-formula><tex-math>$mathbf{%}$</tex-math></inline-formula>\u0000 reduction in the projected device longevity. This work proposes an alternative strategy for power-optimized LLPM synchronization, which is based on synchronous duty-cycling of the transceivers and direct-digital CIC (DD-CIC). In line with this strategy, a novel low-power DD-CIC receiver for short-packet communication based on Manchester-encoded data and with fast startup time is presented. The circuit was fabricated in 180 nm CMOS technology and analyzed with respect to sensitivity, current consumption and startup time under highly duty-cycled operation. The receiver achieves a sensitivity of 81.6\u0000<inline-formula><tex-math>$mathbf{pm}$</tex-math></inline-formula>\u00007.4 \u0000<inline-formula><tex-math>$mu$</tex-math></inline-formula>\u0000V at a data rate of 100 kb/s, with an active current consumption of 39.1\u0000<inline-formula><tex-math>$mathbf{pm}$</tex-math></inline-formula>\u00000.6 \u0000<inline-formula><tex-math>$mu$</tex-math></inline-formula>\u0000A and a startup time below 250 \u0000<inline-formula><tex-math>$mathbf{mu}$</tex-math></inline-formula>\u0000s. Operating the receiver as specified by the proposed LLPM synchronization strategy reduces the current consumption to a measured average value of 73 nA. In conclusion, this work suggests synchronous duty-cycling for CIC-based implant synchronization as a promising concept to severely reduce the current consumption of contemporary dual-chamber LLPMs. Consequently, device longevity may be increased significantly, potentially reducing the frequency of costly and complication-prone re-interventions.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 6","pages":"1338-1353"},"PeriodicalIF":0.0,"publicationDate":"2024-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10504651","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140614807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}