IEEE transactions on biomedical circuits and systems最新文献_第2页

A Differential Impedance Flow Cytometry Front-End with Baseline Current Cancellation. 差分阻抗流式细胞仪前端与基线电流消除。

IEEE transactions on biomedical circuits and systems Pub Date : 2025-07-01 DOI: 10.1109/TBCAS.2025.3585089

Siyuan Yu, Louis Marun, Matthew L Johnston

{"title":"A Differential Impedance Flow Cytometry Front-End with Baseline Current Cancellation.","authors":"Siyuan Yu, Louis Marun, Matthew L Johnston","doi":"10.1109/TBCAS.2025.3585089","DOIUrl":"https://doi.org/10.1109/TBCAS.2025.3585089","url":null,"abstract":"In this work, we present a high-performance analog front-end (AFE) circuit for impedance-based flow cytometry readout. The AFE is designed to interface to a three-electrode sensor topology using center electrode excitation and differential current output. To satisfy the needs of a differential high gain signal path, we propose a digitally tunable and calibrated cancellation current generation path to remove the baseline current injected into the transimpedance amplifier (TIA) stages. This prevents TIA saturation and allows for higher gain. Consequently, the AFE is more power efficient while maintaining better noise and interference rejection. The proposed circuit is designed and fabricated in a 180nm CMOS process. It covers an excitation frequency range of 0.5MHz to 10MHz and consumes 15.6mW during nominal operation. Digital calibration is implemented using an off-chip ADC and automated calibration algorithm. Measurement results show that at 1MHz excitation, the AFE achieves $1.7 text{pA}/sqrt{text{Hz}}$ input-referred current noise density with floating inputs. The AFE achieves detection of 3um diameter particles in a microfluidic flow cell, demonstrating its performance and practicality for impedance flow cytometry.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2025-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144546653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

CMOS LIF Neurons with Local Membrane Dynamic Biasing Based on Reciprocal Inhibition for Self-Oscillatory Neural Networks. 基于互反抑制的自振荡神经网络局部膜动态偏置CMOS LIF神经元。

IEEE transactions on biomedical circuits and systems Pub Date : 2025-06-25 DOI: 10.1109/TBCAS.2025.3583093

Mannhee Cho, Minil Kang, Minseong Um, Hangue Park, Hyung-Min Lee

{"title":"CMOS LIF Neurons with Local Membrane Dynamic Biasing Based on Reciprocal Inhibition for Self-Oscillatory Neural Networks.","authors":"Mannhee Cho, Minil Kang, Minseong Um, Hangue Park, Hyung-Min Lee","doi":"10.1109/TBCAS.2025.3583093","DOIUrl":"https://doi.org/10.1109/TBCAS.2025.3583093","url":null,"abstract":"This paper presents a CMOS-based neuron network that can emulate self-oscillatory biasing behaviors found in biological neural oscillator models. Based on leaky integrate-and-fire (LIF) neuron models, the proposed neuron circuit adopts the concept of reciprocal inhibitory network and synaptic fatigue as well as excitatory drive stimulation for replicating extracellular fluidic biasing of membrane potentials. On top of the base neuron circuit, an excitation integrator integrates positive and negative excitatory input spikes to stimulate the membrane potential bias, and a bias controller receives inhibitory drive input and generates output inhibitory drives depending on the membrane potential bias level. The proposed networks of multiple neurons with inhibitory connections can generate oscillating membrane potential biases, which can be used as local dynamic thresholds for neuron spike firing, resulting in self-patterned output spikes such as switching or dynamic firing rate patterns. The proposed neuron network was implemented with 250-nm CMOS process operating at the supply voltage of 2.5 V and consuming average power of 99.31μW per neuron during full operation. Operation waveforms were measured in various input conditions which can produce multiple output patterns. Variances in output signals due to process variation were measured from 32 neurons to verify the stability of operation, showing the standard deviation of 18% in the membrane potential gain per input spike and 12% in oscillation periods of the membrane potential bias. The results verified that the proposed neuron network can replicate the self-oscillatory behaviors of biological neuron models.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2025-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144499941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 0.66-mm² 0.49 pJ/SOP SNN Processor with Temporal-Spatial Post-Neuron-Processing and Model-Adaptive Crossbar in 40-nm CMOS. 具有时空后神经元处理和模型自适应交叉棒的40nm CMOS 0.66 mm2 0.49 pJ/SOP SNN处理器。

IEEE transactions on biomedical circuits and systems Pub Date : 2025-06-24 DOI: 10.1109/TBCAS.2025.3582246

Jinqiao Yang, Zikai Zhu, Haoming Chu, Anqin Xiao, Yuxiang Huan, Lirong Zheng, Zhuo Zou

{"title":"A 0.66-mm2 0.49 pJ/SOP SNN Processor with Temporal-Spatial Post-Neuron-Processing and Model-Adaptive Crossbar in 40-nm CMOS.","authors":"Jinqiao Yang, Zikai Zhu, Haoming Chu, Anqin Xiao, Yuxiang Huan, Lirong Zheng, Zhuo Zou","doi":"10.1109/TBCAS.2025.3582246","DOIUrl":"https://doi.org/10.1109/TBCAS.2025.3582246","url":null,"abstract":"This paper presents a Spiking Neural Network (SNN) processor specifically designed to overcome the limitations of existing parallel architectures in maintaining high energy efficiency and model adaptability in a compact area footprint for Artificial Intelligence of Things (AIoT). This is achieved through two key design features: a Temporal-Spatial Post-Neuron Processing (PoNP) scheme that efficiently reuses membrane potential, maximizes parallelism, and reduces memory bank requirements; and a Model-Adaptive Crossbar design with preconfigured parameters and a dynamic switching mechanism enables processing of various SNN models through operation orchestration without efficiency degradation. Using an 8-way parallel pipeline design, the processor achieves a throughput of 128 Synaptic Operations (SOPs) per cycle, resulting in a 2.8× enhancement in energy efficiency. Fabricated in a 40-nm CMOS process, the chip occupies a compact core area of 0.66 mm2. It achieves a power consumption of 6.26 mW, an energy efficiency of 0.49 pJ/SOP, and a throughput of 12.8 GSOPS/s at 0.75 V, 100 MHz. The chip is evaluated using typical spatial, temporal, and temporal-spatial datasets, including MIT-BIH, MNIST, N-MNIST, NavGesture, and SHD. These results demonstrate that our chip achieves best-in-class in terms of energy efficiency and latency compared to state-of-the-art architectures.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144487501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

System-on-Chip for Flow Cytometry With Impedance Measurement and Integrated Real-Time Size Classification 片上系统流式细胞仪与阻抗测量和集成的实时尺寸分类。

IF 4.9

IEEE transactions on biomedical circuits and systems Pub Date : 2025-06-04 DOI: 10.1109/TBCAS.2025.3576317

Tzu-Hsuan Chou;Siyuan Yu;Calder Wilson;Jacob Dawes;Jaehyeong Park;Louis Marun;Matthew L. Johnston

{"title":"System-on-Chip for Flow Cytometry With Impedance Measurement and Integrated Real-Time Size Classification","authors":"Tzu-Hsuan Chou;Siyuan Yu;Calder Wilson;Jacob Dawes;Jaehyeong Park;Louis Marun;Matthew L. Johnston","doi":"10.1109/TBCAS.2025.3576317","DOIUrl":"10.1109/TBCAS.2025.3576317","url":null,"abstract":"This paper presents an impedance measurement system-on-chip (SoC) for flow cytometry (i.e. cell counting) applications. A source-differential, three-electrode sensing scheme is used in a microfluidic flow cell for particle detection. At the front-end, a lock-in amplifier architecture is used, including a high-gain TIA with 60 MHz bandwidth, passive mixers, and low-pass filters. The ac sensor signal is demodulated to extract in-phase (I) and quadrature (Q) baseband components to measure complex impedance. At the back-end, the SoC includes an 8-bit level-crossing ADC (LCADC) for digitizing I/Q signals, followed by real-time digital feature extraction and linear classification for real-time cell size determination. The SoC was fabricated in a 180 nm CMOS process. A measured prototype IC achieves 733 fA/<inline-formula><tex-math>$sqrt{Hz}$</tex-math></inline-formula> noise floor and 23 pArms input-referred noise from 1-1 kHz. Combined with a microfluidic flow cell, polymer beads in solution were used as cell surrogates to demonstrate particle counting. Measured results for particle diameters of 10 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m, 6 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m, 4.5 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m and 3 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m are shown. Following offline training, the SoC demonstrated on-chip classification of 4.5 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m and 6 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m beads with a prediction accuracy of 86.16% with pre-recorded data, and 73.6 % while performing real-time inline classification.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 4","pages":"712-725"},"PeriodicalIF":4.9,"publicationDate":"2025-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144228062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 96 dB Input Dynamic Range Galvanic Skin Response Readout IC with 3.5 pArms Input-Referred Noise for Mental Stress Monitoring. 一种96 dB输入动态范围皮肤电响应读出IC， 3.5 pArms输入参考噪声，用于精神压力监测。

IEEE transactions on biomedical circuits and systems Pub Date : 2025-05-26 DOI: 10.1109/TBCAS.2025.3573614

Yi-Jie Lin, Lin Chou, Kun-Ju Tsai, Yu-Te Liao

引用次数: 0

A 0.48° Phase Error 91.1dB SNR Bioimpedance Measurement IC for Monitoring Cardiopulmonary Diseases. 用于心肺疾病监测的0.48°相位误差91.1dB信噪比生物阻抗测量芯片。

IEEE transactions on biomedical circuits and systems Pub Date : 2025-05-21 DOI: 10.1109/TBCAS.2025.3572374

Jiarun Yuan, Yanxing Suo, Qiao Cai, Hui Wang, Yongfu Li, Yong Lian, Yang Zhao

{"title":"A 0.48° Phase Error 91.1dB SNR Bioimpedance Measurement IC for Monitoring Cardiopulmonary Diseases.","authors":"Jiarun Yuan, Yanxing Suo, Qiao Cai, Hui Wang, Yongfu Li, Yong Lian, Yang Zhao","doi":"10.1109/TBCAS.2025.3572374","DOIUrl":"https://doi.org/10.1109/TBCAS.2025.3572374","url":null,"abstract":"This article presents a low-power and low phase error bioimpedance (BioZ) measurement IC designed for monitoring cardiopulmonary diseases. To compensate for the phase shift introduced along the signal path by current generator (CG), electrodes and sensor analog front-end (AFE), a novel phase shift calibration logic is proposed. Utilizing this calibration logic, a single-channel in-phase demodulation-based impedance measurement scheme is developed. A noise shaping pseudo-sine wave CG with data-weighted averaging (DWA) is used to minimize modulation harmonics. Fabricated in a 0.18μm CMOS process, the chip occupies 0.73mm2 and consumes between 52.7 to 97.5μA current from a 1.8V supply. The CG achieves 74.1dB SFDR and -70dB THD at 15.5kHz with a 50μApk stimulation current. The chip achieves $2 text{m} Omega / sqrt{} Hz$ input-referred impedance noise at 1Hz, 91.1dB SNR (BW=4Hz), $36 text{k} Omega$ input range and less than 0.48° phase error (0-90°, 1-20kHz). On-body BioZ experiments using a 4-electrode configuration demonstrate clear recordings of Impedance Cardiography (ICG) and respiration signals.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2025-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144121784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

From Wearables to Implantables: Harnessing sensor technologies for continuous health monitoring. 从可穿戴设备到植入式设备：利用传感器技术进行持续健康监测。

IEEE transactions on biomedical circuits and systems Pub Date : 2025-05-09 DOI: 10.1109/TBCAS.2025.3568754

Asish Koruprolu, Tyler Hack, Omid Ghadami, Aditi Jain, Drew A Hall

引用次数: 0

Artifact-Tolerant Electrophysiological Sensor Interface with 3.6V/1.8V DM/CM Input Range and 52.3mV_pp/μs Recovery Using Asynchronous Signal Folding. 具有3.6V/1.8V DM/CM输入范围和52.3mVpp/μs异步信号折叠恢复的伪影容电生理传感器接口。

IEEE transactions on biomedical circuits and systems Pub Date : 2025-05-06 DOI: 10.1109/TBCAS.2025.3567524

Qiao Cai, Xinzi Xu, Yanxing Suo, Guanghua Qian, Yongfu Li, Guoxing Wang, Yong Lian, Yang Zhao

{"title":"Artifact-Tolerant Electrophysiological Sensor Interface with 3.6V/1.8V DM/CM Input Range and 52.3mVpp/μs Recovery Using Asynchronous Signal Folding.","authors":"Qiao Cai, Xinzi Xu, Yanxing Suo, Guanghua Qian, Yongfu Li, Guoxing Wang, Yong Lian, Yang Zhao","doi":"10.1109/TBCAS.2025.3567524","DOIUrl":"https://doi.org/10.1109/TBCAS.2025.3567524","url":null,"abstract":"In the practical implementations of wearable sensors, motion artifacts with large amplitudes often cause signal chain saturation, significantly degrading biopotential signal integrity. Similarly, rapid stimulation artifacts are inevitable during closed-loop brain stimulation therapy, posing additional challenges for real-time signal acquisition. To address motion and stimulation artifacts with amplitudes reaching hundreds of mV while minimizing information loss, a sensor interface with high input range and fast artifacts recovery capability is essential. This paper presents a continuous-time track-and-zoom (CT-TAZ) technique designed to handle large artifacts events without saturation. The proposed system achieves a 3.6V/1.8V differential-mode/common-mode full-scale input range. Fabricated in a 180nm CMOS process, the prototype chip occupies an area of 0.694mm2 and consumes 12/32.6/51.6μW for recordings without/with single-end/ with differential rail-to-rail artifacts. The system demonstrates an average artifacts recovery time of 65.3 μs under 3.6V stimulation artifacts, achieving an average artifacts recovery speed of 52.3mVpp/μs, which is 2.25× larger input range and 3× faster recovery compared to the state-of-the-art.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2025-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143995414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Stochastic Signal Processing Based Stimulation Artifact Cancellation in $DeltaSigma$ Neural Frontend 基于随机信号处理的ΔΣ神经前端刺激伪影消除。

IF 4.9

IEEE transactions on biomedical circuits and systems Pub Date : 2025-04-22 DOI: 10.1109/TBCAS.2025.3563684

Gayas Mohiuddin Sayed;Armin Bartels;Daniel De Dorigo;Tim Fleiner;Nicole Rosskothen-Kuhl;Matthias Kuhl

{"title":"Stochastic Signal Processing Based Stimulation Artifact Cancellation in $DeltaSigma$ Neural Frontend","authors":"Gayas Mohiuddin Sayed;Armin Bartels;Daniel De Dorigo;Tim Fleiner;Nicole Rosskothen-Kuhl;Matthias Kuhl","doi":"10.1109/TBCAS.2025.3563684","DOIUrl":"10.1109/TBCAS.2025.3563684","url":null,"abstract":"This paper presents a neural recorder frontend featuring electrical stimulation artifact cancellation by employing an adaptive LMS filter in the stochastic domain. The recording system comprises of a low-noise analog frontend and a 1st-order <inline-formula><tex-math>$DeltaSigma$</tex-math></inline-formula> modulator. A power-efficient stochastic signal processor, occupying an area of 0.12 mm2, processes the <inline-formula><tex-math>$DeltaSigma$</tex-math></inline-formula> modulator output bitstream to learn and compensate for artifacts induced by concurrent electrical stimulation. The proposed approach, validated on a prototype ASIC fabricated in 180 nm CMOS technology, has a total power consumption of 6.83 <inline-formula><tex-math>$boldsymbol{mu}$</tex-math></inline-formula>W, with the stochastic signal processor consuming only 0.51 <inline-formula><tex-math>$boldsymbol{mu}$</tex-math></inline-formula>W. Experimental results demonstrate that the system effectively suppresses peak-to-peak stimulation artifacts of 200 mV by approximately 33 dB over a 10 kHz bandwidth, establishing it as a novel state-of-the-art real-time artifact cancellation system. Furthermore, in-vitro validation for both biphasic and monophasic stimulation confirms its efficacy, with 74.3 mVpp artifacts from biphasic stimulation being attenuated by 25 dB.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 4","pages":"701-711"},"PeriodicalIF":4.9,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144056116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 101-dB DR 2.2GΩ-Input-Impedance Direct Digitization ExG Front-End With Δ-Modulation. 101-dB DR 2.2GΩ-Input-Impedance直接数字化ExG前端与Δ-Modulation。

IEEE transactions on biomedical circuits and systems Pub Date : 2025-04-21 DOI: 10.1109/TBCAS.2025.3563304

Yuying Li, Hao Li, Tianxiang Qu, Qi Liu, Zhiliang Hong, Jiawei Xu

{"title":"A 101-dB DR 2.2GΩ-Input-Impedance Direct Digitization ExG Front-End With Δ-Modulation.","authors":"Yuying Li, Hao Li, Tianxiang Qu, Qi Liu, Zhiliang Hong, Jiawei Xu","doi":"10.1109/TBCAS.2025.3563304","DOIUrl":"https://doi.org/10.1109/TBCAS.2025.3563304","url":null,"abstract":"Long-term, continuous health monitoring imposes stringent demands on bio-recording analog front-end (AFE) circuits, specifically in terms of dynamic range (DR), noise, input impedance, and power consumption. This work introduces a DR-enhanced direct-digitization AFE based on a Δ-modulated transconductor (TC) stage, followed by a second-order ΔΣ ADC. In this architecture, the accumulated DAC is subtracted exclusively at the TC input stage, allowing the integrators to process only the low-amplitude Δ-modulated signal and thus relaxing the dynamic range constraints of conventional Gm-C ΔΣ ADCs. The TC input stage achieves high input impedance and high linearity through a current-balancing transconductor and a flipped-voltage-follower (FVF) loop. Fabricated with a standard 180nm CMOS process, the proposed Δ-ΔΣ AFE exhibits an SNDR of 91 dB, a dynamic range of 101 dB, input referred noise of 58 nV/√Hz, and a power consumption of 63 μW. These results correspond to a FoMSNDR of 160.1 dB and a FoMDR of 170 dB. The AFE prototype has been validated through scalp EEG, leg EMG, and chest ECG with significant body movements, demonstrating its effectiveness as a motion-artifact-tolerant direct-ADC front end.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144052464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0