2019 Symposium on VLSI Technology最新文献_第3页

Technology challenges and enablers to extend Cu metallization to beyond 7 nm node 将铜金属化扩展到7nm以上节点的技术挑战和推动因素

2019 Symposium on VLSI Technology Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776573

T. Nogami, H. Huang, H. Shobha, R. Patlolla, J. Kelly, C. Penny, C. Hu, D. Sil, S. DeVries, J. Lee, S. Nguyen, L. Jiang, J. Demarest, J. Li, G. Lian, M. Ali, P. Bhosale, N. Lanzillo, K. Motoyama, S. Lian, T. Standaert, G. Bonilla, D. Edelstein, B. Haran

{"title":"Technology challenges and enablers to extend Cu metallization to beyond 7 nm node","authors":"T. Nogami, H. Huang, H. Shobha, R. Patlolla, J. Kelly, C. Penny, C. Hu, D. Sil, S. DeVries, J. Lee, S. Nguyen, L. Jiang, J. Demarest, J. Li, G. Lian, M. Ali, P. Bhosale, N. Lanzillo, K. Motoyama, S. Lian, T. Standaert, G. Bonilla, D. Edelstein, B. Haran","doi":"10.23919/VLSIT.2019.8776573","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776573","url":null,"abstract":"Electromigration (EM) and TDDB reliability of Cu interconnects with a barrier/wetting layer as thin as 2 nm employing a PVD-reflowed through-Co self-forming barrier (tCoSFB) is demonstrated to meet the required specifications for 7 nm BEOL. The resulting Cu EM lifetime is 2000X longer than Cu interconnects with a standard scaled barrier/wetting layer. This tCoSFB Cu EM and TDDB reliability performance were equivalent to pure Co metal interconnects, but with a 50% lower line resistance even down to 30 nm pitch dimensions. However, the annealing process for PVD-reflow Cu seed that enhances EM reliability caused Cu agglomeration at dual damascene line-end vias, leading to poor via-chain yield. Resolving this geometry-sensitive via-fill problem was identified as key to extending Cu manufacturability to 7 nm and beyond. We propose, and show preliminary data, for Cu/tCoSFB metallization with CVD Co via pre-fill as potential solution.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"51 1","pages":"T18-T19"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73962392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Inference of Long-Short Term Memory networks at software-equivalent accuracy using 2.5M analog Phase Change Memory devices 使用2.5M模拟相变存储器器件在软件等效精度下推断长短期记忆网络

2019 Symposium on VLSI Technology Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776519

H. Tsai, S. Ambrogio, C. Mackin, P. Narayanan, R. Shelby, K. Rocki, A. Chen, G. Burr

引用次数: 26

Split-Gate FeFET (SG-FeFET) with Dynamic Memory Window Modulation for Non-Volatile Memory and Neuromorphic Applications 分栅ffet (sg - ffet)与动态记忆窗调制非易失性记忆和神经形态应用

2019 Symposium on VLSI Technology Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776555

V. Hu, Hung-Han Lin, Z. Zheng, Zih-Tang Lin, Yi-chun Lu, Lun-Yi Ho, Yen-Wei Lee, Cheng-Wei Su, C. Su

{"title":"Split-Gate FeFET (SG-FeFET) with Dynamic Memory Window Modulation for Non-Volatile Memory and Neuromorphic Applications","authors":"V. Hu, Hung-Han Lin, Z. Zheng, Zih-Tang Lin, Yi-chun Lu, Lun-Yi Ho, Yen-Wei Lee, Cheng-Wei Su, C. Su","doi":"10.23919/VLSIT.2019.8776555","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776555","url":null,"abstract":"In this work, we propose a novel split-gate FeFET (SG-FeFET) with two separate external gates to dynamically modulate the memory window (MW) for non-volatile memory and neuromorphic applications. During read operation, only one gate is turned on to decrease the area ratio $(text{A}_{text{FE}}/text{A}_{text{IL}})$ of ferroelectric layer to insulator layer, which increases MW and read current ratio $(text{I}_{text{Read}_{-}1}/text{I}_{text{Read}_{-}0})$. During write operation (program/erase), both two gates are turned on to increase $text{A}_{text{FE}}/text{A}_{text{IL}}$, which decreases MW, thereby resulting in lower write voltage $(text{V}_{text{Write}})$. Compared to FeFET, SG-FeFET (1) Demonstrates lower $text{V}_{text{Write}}(=1.85text{V})$ and 59.5% reduction in write energy at fixed $text{I}_{text{Read}_{-}1}/text{I}_{text{Read}_{-}0};(2)$ Exhibits lower read energy (-11.3%) and higher $text{I}_{text{Read}_{-}text{1}/text{I}_{text{Read}_{-}0}}(=8.6text{E}6)$ at fixed $text{V}_{text{Write}};(3)$ Allows random access and eliminates half-select disturb; (4) Preserves higher endurance due to lower $text{V}_{text{Write}}$ and charge trapping. SG-FeFET as synaptic device also exhibits superior symmetry and linearity for potentiation and depression process.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"68 1","pages":"T134-T135"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82492259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Advantage of Extremely-thin Body (Tsi~3nm) Device to Boost the Memory Window for 3D NAND Flash 超薄体(Tsi~3nm)器件的优势提升3D NAND闪存的存储窗口

2019 Symposium on VLSI Technology Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776483

H. Lue, C. Hsieh, T. Hsu, W. C. Chen, C. Chen, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu

引用次数: 6

7nm Mobile SoC and 5G Platform Technology and Design Co-Development for PPA and Manufacturability 7nm移动SoC和5G平台技术与设计共同开发，用于PPA和可制造性

2019 Symposium on VLSI Technology Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776511

M. Cai, Hyunwoo Park, Jackie Yang, Youseok Suh, Jun Chen, Yandong Gao, Lunwei Chang, John Zhu, S. C. Song, Jihong Choi, Gary Chen, Bo Yu, Xiao-Yong Wang, V. Huang, Gudoor Reddy, Nagaraj Kelageri, D. Kidd, P. Pénzes, W. Chung, S. Yang, S.B. Lee, B. Tien, G. Nallapati, S. Wu, P. Chidambaram

引用次数: 3

1 Kbit 6T SRAM Arrays in Carbon Nanotube FET CMOS 碳纳米管FET CMOS中的1kbit 6T SRAM阵列

2019 Symposium on VLSI Technology Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776563

P. Kanhaiya, C. Lau, G. Hills, M. Bishop, M. Shulaker

引用次数: 11

GaN HEMTs with Breakdown Voltage of 2200 V Realized on a 200 mm GaN-on-Insulator(GNOI)-on-Si Wafer 在200 mm的绝缘体上氮化镓硅片上实现了击穿电压为2200 V的氮化镓hemt

2019 Symposium on VLSI Technology Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776522

Zhihong Liu, Hanlin Xie, K. Lee, C. S. Tan, G. Ng, E. Fitzgerald

引用次数: 1

A Novel Confined Nitride-Trapping Layer Device for 3D NAND Flash with Robust Retention Performances 一种具有鲁棒保留性能的三维NAND闪存受限氮捕获层器件

2019 Symposium on VLSI Technology Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776572

C. Fu, H. Lue, T. Hsu, Wei-Chen Chen, Guan-Ru Lee, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu

引用次数: 6

Monolithic 3D+ -IC based Reconfigurable Compute-in-Memory SRAM Macro 基于单片3D+ ic的可重构内存计算SRAM宏

2019 Symposium on VLSI Technology Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776506

S. Srinivasa, Yung-Ning Tu, Xin Si, Cheng-Xin Xue, Chun-Ying Lee, F. Hsueh, Chane-Hone Shen, J. Shieh, W. Yeh, A. Ramanathan, M. Ho, J. Sampson, Meng-Fan Chang, V. Narayanan

引用次数: 9

In-memory Reinforcement Learning with Moderately-Stochastic Conductance Switching of Ferroelectric Tunnel Junctions 铁电隧道结中随机电导开关的记忆强化学习

2019 Symposium on VLSI Technology Pub Date : 2019-06-09 DOI: 10.23919/VLSIT.2019.8776500

R. Berdan, T. Marukame, S. Kabuyanagi, K. Ota, M. Saitoh, S. Fujii, J. Deguchi, Y. Nishi

引用次数: 16