2019 Symposium on VLSI Technology最新文献_第10页

High Performance GeSn Photodiode on a 200 mm Ge-on-insulator Photonics Platform for Advanced Optoelectronic Integration with Ge CMOS Operating at 2 μm Band 高性能GeSn光电二极管在200毫米绝缘体上的Ge光子平台上，用于先进的光电集成与2 μm波段的Ge CMOS

2019 Symposium on VLSI Technology Pub Date : 2019-06-01 DOI: 10.23919/VLSIT.2019.8776554

Shengqiang Xu, Kaizhen Han, Yi-Chiau Huang, Yuye Kang, S. Masudy‐Panah, Ying Wu, D. Lei, Yunshan Zhao, X. Gong, Y. Yeo

引用次数: 1

SiGe Channel CMOS: Understanding Dielectric Breakdown and Bias Temperature Instability Tradeoffs SiGe通道CMOS:理解介电击穿和偏置温度不稳定性的权衡

2019 Symposium on VLSI Technology Pub Date : 2019-06-01 DOI: 10.23919/VLSIT.2019.8776481

R. Southwick, M. Wang, S. Mochizuki, Xin He Miao, J. Li, C. Lee

引用次数: 2

Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Secuirty Solution in 5G Era 14nm HKMG FinFET平台上的嵌入式PUF:一种适用于5G时代物联网安全解决方案的新型2位otp存储器

2019 Symposium on VLSI Technology Pub Date : 2019-01-01 DOI: 10.23919/VLSIT.2019.8776515

E. Hsieh, H. W. Wang, C. H. Liu, S. Chung, T. P. Chen, S.A. Huang, T. J. Chen, O. Cheng

引用次数: 7

A Comprehensive Kinetical Modeling of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Energy Effects on Negative Capacitance FETs 铁电介质多晶相分布的综合动力学建模及界面能对负电容场效应管的影响

2019 Symposium on VLSI Technology Pub Date : 2019-01-01 DOI: 10.23919/VLSIT.2019.8776508

Y. Tang, Che-Lun Fan, Ya-Chen Kao, N. Módolo, C. Su, T.-L. Wu, K. Kao, Pin-Jiun Wu, S.-W. Hsaio, A. Useinov, P. Su, W. Wu, G. Huang, J. Shieh, W. Yeh, Y. Wang

引用次数: 7

First Vertically Stacked, Compressively Strained, and Triangular Ge0.91Sn0.09pGAAFETs with High $mathbf{I_{ON}}$ of $mathbf{19.3}mu mathbf{A} mathbf{at} mathbf{V_{OV}}=mathbf{V}_{mathbf{DS}}=mathbf{-0.5V}, mathbf{G}_{mathbf{m}}$ of $mathbf{50.2}mu mathbf{S}$ at $mathbf{V_{DS}}=mat 第一个垂直叠加，压缩压缩和三角形Ge0.91Sn0.09pGAAFETs，高$mathbf{I_{ON}}$ $mathbf{19.3}mu mathbf{A} mathbf{at} mathbf{V_{OV}}=mathbf{V}} {mathbf{DS}}=mathbf{-0.5V}， $mathbf{G} {mathbf{m}}$ $mathbf{50.2}mu mathbf{S}$ at $mathbf{V_{DS}}=mat

2019 Symposium on VLSI Technology Pub Date : 2019-01-01 DOI: 10.23919/VLSIT.2019.8776550

Yu-Shiang Huang, Hung-Yu Ye, Fang-Liang Lu, Yi-Chun Liu, Chien-Te Tu, Chung-yi Lin, Shih-Ya Lin, Sun-Rang Jan, C. W. Liu

{"title":"First Vertically Stacked, Compressively Strained, and Triangular Ge0.91Sn0.09pGAAFETs with High $mathbf{I_{ON}}$ of $mathbf{19.3}mu mathbf{A} mathbf{at} mathbf{V_{OV}}=mathbf{V}_{mathbf{DS}}=mathbf{-0.5V}, mathbf{G}_{mathbf{m}}$ of $mathbf{50.2}mu mathbf{S}$ at $mathbf{V_{DS}}=mat","authors":"Yu-Shiang Huang, Hung-Yu Ye, Fang-Liang Lu, Yi-Chun Liu, Chien-Te Tu, Chung-yi Lin, Shih-Ya Lin, Sun-Rang Jan, C. W. Liu","doi":"10.23919/VLSIT.2019.8776550","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776550","url":null,"abstract":"The natural etching stop on {111} facets yields the small dangling bond density and roughness, enabling low SS and high <tex>$text{I}_{text{ON}}$</tex> on {111} sidewalls of the GAA channels. In addition, the <tex>$sim 2%$</tex> uniaxial compressive strain and <tex>$[text{Sn}]=9%$</tex> in the channel can reduce the hole effective mass. As a result, 50% improvement of <tex>$text{I}_{text{ON}}= 120mu text{A}/mutext{m}$</tex> (perimeter), and 71% improvement of <tex>$text{G}_{text{m}}=312mu text{S}/mutext{m}$</tex> are achieved than our previous 3 stacked GeSn {001} nanosheets. Record high <tex>$text{I}_{text{ON}}$</tex> of <tex>$19.3mu text{A}$</tex> per stack at <tex>$text{V}_{text{OV}}=text{V}_{DS}=-0.5text{V}$</tex> and record <tex>$text{G}_{text{m}}$</tex> of <tex>$50.2mutext{S}$</tex> per stack at <tex>$text{V}_{text{DS}}=-0.5text{V}$</tex> among all GeSn FinFETs and GAAFETs are achieved. The <tex>$text{SS}_{text{lin}}$</tex> as low as S4mV/dec is also obtained, 22% reduction than our previous work.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"1 1","pages":"T180-T181"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88690183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Negative Capacitance CMOS Field-Effect Transistors with Non-Hysteretic Steep Sub-60mV/dec Swing and Defect-Passivated Multidomain Switching 负电容CMOS场效应晶体管的非迟滞陡摆幅和缺陷钝化多域开关

2019 Symposium on VLSI Technology Pub Date : 2019-01-01 DOI: 10.23919/VLSIT.2019.8776482

Chien Liu, Hsuan-Han Chen, Chih-Chieh Hsu, C. Fan, H. Hsu, Chun‐Hu Cheng

引用次数: 8

A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 1012 Endurance 在2.5ns ppm时间和1012续航时间的纯逻辑FinFET平台上构建理想线性神经形态突触的新架构

2019 Symposium on VLSI Technology Pub Date : 2019-01-01 DOI: 10.23919/VLSIT.2019.8776488

E. Hsieh, H. Chang, S. Chung, T. P. Chen, S. A. Huang, T. J. Chen, O. Cheng, S. Wong

{"title":"A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 1012 Endurance","authors":"E. Hsieh, H. Chang, S. Chung, T. P. Chen, S. A. Huang, T. J. Chen, O. Cheng, S. Wong","doi":"10.23919/VLSIT.2019.8776488","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776488","url":null,"abstract":"In this work, we will explore pure logic FinFET devices to realize the functionality of linear weight tuning capability as electric synapses. The unit cell of this new FinFET synapse is composed of two identical FinFETs in series; one serves as control and the other one as storage. This new FinFET synapse exhibits ideal linearity with nearly infinity training cycles $(> 10^{12})$, much lower programming voltage, 0.85V, and faster speed, 2.5ns. It can also analogically increase or decrease the transistor's $text{v}_{text{th}}$ to vary the drain conductance. As far as the analog performance is concerned, it performs excellent linearity and a wide tuning-window (20x) of weight-tuning capability. lkb synaptic array has also been designed. The spice-simulated results have shown that new FinFET synaptic array can expand the array-size to 64×64, exhibiting 300x of SNR, w.r.t. that of RRAM array. Finally, the training of the neural network based on the proposed FinFET synapse can achieve 97.43% accuracy as high as the GPU one does.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"11 1","pages":"T138-T139"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78828366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Sunday Workshops 周日研讨会

2019 Symposium on VLSI Technology Pub Date : 2019-01-01 DOI: 10.23919/VLSIT.2019.8776524

引用次数: 0

The physical layer of ambient intelligence 环境智能的物理层

2019 Symposium on VLSI Technology Pub Date : 2005-04-25 DOI: 10.1109/VTSA.2005.1497061

H. Houten

引用次数: 2

70 nm fully-depleted SOI CMOS using a new fabrication scheme: the spacer/replacer scheme 70nm全耗尽SOI CMOS采用新的制造方案:间隔/替换方案

2019 Symposium on VLSI Technology Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015438

H. Meer, K. Meyer

引用次数: 9