70 nm fully-depleted SOI CMOS using a new fabrication scheme: the spacer/replacer scheme

Abstract

High-performance fully-depleted SOI CMOS transistors have been realized on a 28 nm ultra thin silicon substrate with a physical gate length of 70 nm and a post NO-annealed gate oxide of 1.4 nm. A new fabrication scheme, the spacer/replacer scheme, has been used to optimize the device performance of the ultra thin-film SOI transistors. Excellent device performance has been obtained: I/sub on/ equals 711 /spl mu/A//spl mu/m and 350 /spl mu/A//spl mu/m at I/sub off/=16 nA//spl mu/m for nMOS and pMOS, respectively. The unloaded ring oscillator gate-delay is 14.5 ps at V/sub DD/=1.2 V.