V. Hu, Hung-Han Lin, Z. Zheng, Zih-Tang Lin, Yi-chun Lu, Lun-Yi Ho, Yen-Wei Lee, Cheng-Wei Su, C. Su
{"title":"Split-Gate FeFET (SG-FeFET) with Dynamic Memory Window Modulation for Non-Volatile Memory and Neuromorphic Applications","authors":"V. Hu, Hung-Han Lin, Z. Zheng, Zih-Tang Lin, Yi-chun Lu, Lun-Yi Ho, Yen-Wei Lee, Cheng-Wei Su, C. Su","doi":"10.23919/VLSIT.2019.8776555","DOIUrl":null,"url":null,"abstract":"In this work, we propose a novel split-gate FeFET (SG-FeFET) with two separate external gates to dynamically modulate the memory window (MW) for non-volatile memory and neuromorphic applications. During read operation, only one gate is turned on to decrease the area ratio $(\\text{A}_{\\text{FE}}/\\text{A}_{\\text{IL}})$ of ferroelectric layer to insulator layer, which increases MW and read current ratio $(\\text{I}_{\\text{Read}_{-}1}/\\text{I}_{\\text{Read}_{-}0})$. During write operation (program/erase), both two gates are turned on to increase $\\text{A}_{\\text{FE}}/\\text{A}_{\\text{IL}}$, which decreases MW, thereby resulting in lower write voltage $(\\text{V}_{\\text{Write}})$. Compared to FeFET, SG-FeFET (1) Demonstrates lower $\\text{V}_{\\text{Write}}(=1.85\\text{V})$ and 59.5% reduction in write energy at fixed $\\text{I}_{\\text{Read}_{-}1}/\\text{I}_{\\text{Read}_{-}0};(2)$ Exhibits lower read energy (-11.3%) and higher $\\text{I}_{\\text{Read}_{-}\\text{1}/\\text{I}_{\\text{Read}_{-}0}}(=8.6\\text{E}6)$ at fixed $\\text{V}_{\\text{Write}};(3)$ Allows random access and eliminates half-select disturb; (4) Preserves higher endurance due to lower $\\text{V}_{\\text{Write}}$ and charge trapping. SG-FeFET as synaptic device also exhibits superior symmetry and linearity for potentiation and depression process.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"68 1","pages":"T134-T135"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIT.2019.8776555","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
In this work, we propose a novel split-gate FeFET (SG-FeFET) with two separate external gates to dynamically modulate the memory window (MW) for non-volatile memory and neuromorphic applications. During read operation, only one gate is turned on to decrease the area ratio $(\text{A}_{\text{FE}}/\text{A}_{\text{IL}})$ of ferroelectric layer to insulator layer, which increases MW and read current ratio $(\text{I}_{\text{Read}_{-}1}/\text{I}_{\text{Read}_{-}0})$. During write operation (program/erase), both two gates are turned on to increase $\text{A}_{\text{FE}}/\text{A}_{\text{IL}}$, which decreases MW, thereby resulting in lower write voltage $(\text{V}_{\text{Write}})$. Compared to FeFET, SG-FeFET (1) Demonstrates lower $\text{V}_{\text{Write}}(=1.85\text{V})$ and 59.5% reduction in write energy at fixed $\text{I}_{\text{Read}_{-}1}/\text{I}_{\text{Read}_{-}0};(2)$ Exhibits lower read energy (-11.3%) and higher $\text{I}_{\text{Read}_{-}\text{1}/\text{I}_{\text{Read}_{-}0}}(=8.6\text{E}6)$ at fixed $\text{V}_{\text{Write}};(3)$ Allows random access and eliminates half-select disturb; (4) Preserves higher endurance due to lower $\text{V}_{\text{Write}}$ and charge trapping. SG-FeFET as synaptic device also exhibits superior symmetry and linearity for potentiation and depression process.