T. Nogami, H. Huang, H. Shobha, R. Patlolla, J. Kelly, C. Penny, C. Hu, D. Sil, S. DeVries, J. Lee, S. Nguyen, L. Jiang, J. Demarest, J. Li, G. Lian, M. Ali, P. Bhosale, N. Lanzillo, K. Motoyama, S. Lian, T. Standaert, G. Bonilla, D. Edelstein, B. Haran
{"title":"将铜金属化扩展到7nm以上节点的技术挑战和推动因素","authors":"T. Nogami, H. Huang, H. Shobha, R. Patlolla, J. Kelly, C. Penny, C. Hu, D. Sil, S. DeVries, J. Lee, S. Nguyen, L. Jiang, J. Demarest, J. Li, G. Lian, M. Ali, P. Bhosale, N. Lanzillo, K. Motoyama, S. Lian, T. Standaert, G. Bonilla, D. Edelstein, B. Haran","doi":"10.23919/VLSIT.2019.8776573","DOIUrl":null,"url":null,"abstract":"Electromigration (EM) and TDDB reliability of Cu interconnects with a barrier/wetting layer as thin as 2 nm employing a PVD-reflowed through-Co self-forming barrier (tCoSFB) is demonstrated to meet the required specifications for 7 nm BEOL. The resulting Cu EM lifetime is 2000X longer than Cu interconnects with a standard scaled barrier/wetting layer. This tCoSFB Cu EM and TDDB reliability performance were equivalent to pure Co metal interconnects, but with a 50% lower line resistance even down to 30 nm pitch dimensions. However, the annealing process for PVD-reflow Cu seed that enhances EM reliability caused Cu agglomeration at dual damascene line-end vias, leading to poor via-chain yield. Resolving this geometry-sensitive via-fill problem was identified as key to extending Cu manufacturability to 7 nm and beyond. We propose, and show preliminary data, for Cu/tCoSFB metallization with CVD Co via pre-fill as potential solution.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"51 1","pages":"T18-T19"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Technology challenges and enablers to extend Cu metallization to beyond 7 nm node\",\"authors\":\"T. Nogami, H. Huang, H. Shobha, R. Patlolla, J. Kelly, C. Penny, C. Hu, D. Sil, S. DeVries, J. Lee, S. Nguyen, L. Jiang, J. Demarest, J. Li, G. Lian, M. Ali, P. Bhosale, N. Lanzillo, K. Motoyama, S. Lian, T. Standaert, G. Bonilla, D. Edelstein, B. Haran\",\"doi\":\"10.23919/VLSIT.2019.8776573\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Electromigration (EM) and TDDB reliability of Cu interconnects with a barrier/wetting layer as thin as 2 nm employing a PVD-reflowed through-Co self-forming barrier (tCoSFB) is demonstrated to meet the required specifications for 7 nm BEOL. The resulting Cu EM lifetime is 2000X longer than Cu interconnects with a standard scaled barrier/wetting layer. This tCoSFB Cu EM and TDDB reliability performance were equivalent to pure Co metal interconnects, but with a 50% lower line resistance even down to 30 nm pitch dimensions. However, the annealing process for PVD-reflow Cu seed that enhances EM reliability caused Cu agglomeration at dual damascene line-end vias, leading to poor via-chain yield. Resolving this geometry-sensitive via-fill problem was identified as key to extending Cu manufacturability to 7 nm and beyond. We propose, and show preliminary data, for Cu/tCoSFB metallization with CVD Co via pre-fill as potential solution.\",\"PeriodicalId\":6752,\"journal\":{\"name\":\"2019 Symposium on VLSI Technology\",\"volume\":\"51 1\",\"pages\":\"T18-T19\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIT.2019.8776573\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIT.2019.8776573","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
采用pvd回流通过co自形成势垒(tCoSFB)的铜互连的电迁移(EM)和TDDB可靠性达到了7纳米BEOL的要求规格。由此产生的Cu EM寿命比具有标准鳞片屏障/润湿层的Cu互连长2000倍。这种tCoSFB Cu EM和TDDB的可靠性性能相当于纯钴金属互连,但即使在30nm间距尺寸下,线路电阻也降低了50%。然而,提高电磁可靠性的pvd -回流铜籽的退火工艺导致铜在双damascene线端过孔处聚集,导致过孔链产率较差。解决这种几何敏感的过孔填充问题被认为是将铜的可制造性扩展到7纳米及以上的关键。我们提出并展示了通过预填充的CVD Co作为潜在解决方案的Cu/tCoSFB金属化的初步数据。
Technology challenges and enablers to extend Cu metallization to beyond 7 nm node
Electromigration (EM) and TDDB reliability of Cu interconnects with a barrier/wetting layer as thin as 2 nm employing a PVD-reflowed through-Co self-forming barrier (tCoSFB) is demonstrated to meet the required specifications for 7 nm BEOL. The resulting Cu EM lifetime is 2000X longer than Cu interconnects with a standard scaled barrier/wetting layer. This tCoSFB Cu EM and TDDB reliability performance were equivalent to pure Co metal interconnects, but with a 50% lower line resistance even down to 30 nm pitch dimensions. However, the annealing process for PVD-reflow Cu seed that enhances EM reliability caused Cu agglomeration at dual damascene line-end vias, leading to poor via-chain yield. Resolving this geometry-sensitive via-fill problem was identified as key to extending Cu manufacturability to 7 nm and beyond. We propose, and show preliminary data, for Cu/tCoSFB metallization with CVD Co via pre-fill as potential solution.