Advantage of Extremely-thin Body (Tsi~3nm) Device to Boost the Memory Window for 3D NAND Flash

H. Lue, C. Hsieh, T. Hsu, W. C. Chen, C. Chen, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu
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引用次数: 6

Abstract

The advantage of using extremely-thin body (ETB, Tsi=3nm) device has been demonstrated in a 3D NAND Flash test chip. Net P/E memory window gain of >1.3V is observed for devices using ETB poly-Si. This substantial gain can be explained by the “quantum confinement” that raises effective Si bandgap and in turn reduces the tunneling barrier height. Simulation model has been validated and it shows equivalent barrier height reduction of ~0.16eV and 0.07eV for electron and hole, respectively for Tsi=3nm. Meanwhile, the extremely-thin body poly silicon channel can improve S.S. to nearly 250mV/dec, which is close to bulk 2D Flash devices. However, the Idsat is degraded to only 160nA for Tsi=3nm, which is attributed to the larger effective mass or higher contact resistance. The degraded Idsat can be accommodated by lower Isense<30nA for page buffer circuit tuning. Random telegraph noise (RTN) is significantly reduced by extremely-thin body, and it shows tighter program-verify (PV) distribution in the MLC/TLC operation.
超薄体(Tsi~3nm)器件的优势提升3D NAND闪存的存储窗口
采用极薄体(ETB, Tsi=3nm)器件的优势已在3D NAND闪存测试芯片中得到验证。对于使用ETB多晶硅的器件,观察到净P/E存储器窗口增益为>1.3V。这种可观的增益可以用“量子约束”来解释,它提高了有效的Si带隙,从而降低了隧道势垒的高度。仿真结果表明,当Tsi=3nm时,电子和空穴的等效势垒高度分别降低了~0.16eV和0.07eV。同时,极薄的多晶硅通道可以将S.S.提高到接近250mV/dec,接近体块2D Flash器件。然而,当Tsi=3nm时,由于更大的有效质量或更高的接触电阻,Idsat仅退化到160nA。降低的Idsat可以通过较低的Isense<30nA进行页面缓冲电路调优。超薄的机身显著降低了随机电报噪声(RTN),并且在MLC/TLC操作中显示出更紧密的程序验证(PV)分布。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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