S. Srinivasa, Yung-Ning Tu, Xin Si, Cheng-Xin Xue, Chun-Ying Lee, F. Hsueh, Chane-Hone Shen, J. Shieh, W. Yeh, A. Ramanathan, M. Ho, J. Sampson, Meng-Fan Chang, V. Narayanan
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Monolithic 3D+ -IC based Reconfigurable Compute-in-Memory SRAM Macro
This paper presents the first monolithic 3D two-layer reconfigurable SRAM macro capable of executing multiple Compute-in-Memory (CiM) tasks as part of data readout. Fabricated using low cost FinFET based 3D+-IC, the SRAM offers concurrent data read from both layers and write from layer 2 with 0.4V $\text{V}_{\text{dd}\min}$ 12.8x improved computation latency is achieved as compared to near memory computation of successive Boolean operations.
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