2012 IEEE 62nd Electronic Components and Technology Conference最新文献

{"title":"Improved predictions of lead free solder joint reliability that include aging effects","authors":"M. Motalab, Z. Cai, J. Suhling, Jiawei Zhang, J. Evans, M. Bozack, P. Lall","doi":"10.1109/ECTC.2012.6248879","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248879","url":null,"abstract":"It has been demonstrated that isothermal aging leads to large reductions (up to 50%) in several key material properties for lead free solders including stiffness (modulus), yield stress, ultimate strength, and strain to failure. In addition, even more dramatic evolution has been observed in the creep response of aged solders, where up to 10,000X increases have been observed in the steady state (secondary) creep strain rate (creep compliance). Such degradations in the stiffness, strength, and creep compliance of the solder material are expected to be universally detrimental to reliability of solder joints in electronic assemblies. Traditional finite element based predictions for solder joint reliability during thermal cycling accelerated life testing are based on solder constitutive equations (e.g. Anand viscoplastic model) and failure models (e.g. energy dissipation per cycle models) that do not evolve with material aging. Thus, there will be significant errors in the calculations with lead free SAC alloys that illustrate dramatic aging phenomena. In our current research, we are developing new reliability prediction procedures that utilize constitutive relations and failure criteria that incorporate aging effects, and then validating the new approaches through correlation with thermal cycling accelerated life testing experimental data. In this paper, we report on the first step of that development, namely the establishment of a revised set of Anand viscoplastic stress-strain relations for solder that include material parameters that evolve with the thermal history of the solder material. The effects of aging on the nine Anand model parameters have been examined by performing stress strain tests on SAC305 samples that were aged for various durations (0-6 months) at a temperature of 100 C. For each aging time, stress-strain data were measured at three strain rates (0.001, 0.0001, and 0.00001 1/sec) and five temperatures (25, 50, 75, 100, and 125 C). Using the measured stress-strain data, the Anand model material parameters have been determined for various aging conditions. Mathematical expressions were then developed to model the evolution of the Anand model parameter with aging time. Our results show that 2 of the 9 constants remain essentially constant during aging, while the other 6 show large changes (30-70%) with up to 6 months of aging at 100 C. Preliminary finite element simulations have also shown that the use of the modified Anand model leads to a strong dependence of the calculated plastic work dissipated per cycle on the aging conditions prior to thermal cycling.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"67 1","pages":"513-531"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89411005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A new approach towards an optimum design and manufacture of microfluidic devices based on ex situ fabricated hydrogel based thin films' integration","authors":"Weiwei Zhao, T. Santaniello, P. Webb, C. Lenardi, Changqing Liu","doi":"10.1109/ECTC.2012.6249114","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249114","url":null,"abstract":"We present a compression based packaging technique which can be applied to reversibly seal hydrogel based materials' thin films and micro-fabricated thermoplastic components for hybrid materials stacking microfluidic cells-based chips design. A multilayer microdevice has been realized for liquid leakage tests at the thermoplastic/hydrogel interface nearby the fluidic circuits machined on the plastic layer; biocompatible Poly-hydroxyethylmethacrylate (PHEMA) hydrogel membranes with different thickness (Ranging from 100 to 200 μm) and micro-milled Polymethylmethacrylate components were chosen to realize the chip. By promoting continuous perfusion of the system pumping aqueous coloured dye solutions in the microchannels, the sealing between the two materials resulted guaranteed for tested flow rate values, ranging from 100nL/min to 10mL/min. Furthermore, to take the hydrogel into operation, a representative case study of a micro-bioreactor based on joint hybrid materials and employing PHEMA thin film as a cell culture substrate has been analyzed and modelled by mean of numerical simulation.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"47 1","pages":"1997-2004"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78411444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"3D stacked microfluidic cooling for high-performance 3D ICs","authors":"Yue Zhang, A. Dembla, Y. Joshi, Muhannad S. Bakir","doi":"10.1109/ECTC.2012.6249058","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249058","url":null,"abstract":"Cooling is a significant challenge for high-performance high-power 3D ICs. hi this paper, we describe the experimental evaluation of 3D ICs with embedded microfluidic cooling. Different architectures are experimentally evaluated ine hiding: 1) a memory-on-processor stack. 2) a processor-on-processor stack with equal power dissipation, and 3) a processor-on-processor stack with different power dissipation, hi all cases, embedded microfluidic cooling shows significant junction temperature reduction compared to air-cooling.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"64 1","pages":"1644-1650"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77937811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Systematic studies of second level interconnection reliability of edge and corner bonded lead-free array-based packages under mechanical and thermal loading","authors":"Hongbin Shi, Daquan Yu, T. Ueda","doi":"10.1109/ECTC.2012.6248953","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248953","url":null,"abstract":"Lead-free (LF) solder joints of portable devices are frequently subjected to unintentional drop, bend, shear and thermal cycling loading during transportation, handling, and usage. Various underfills are widely used in the electronics industry to deal with these challenges, however, the above approaches have some intrinsic shortcomings such as high material costs, low manufacturing assembly rate, poor reworkability and so on. To reduce the cycle time and cost of conventional underfill process, two promising polymeric reinforcement technologies for the next generation array-based package (ABP) application, the so-called edge and corner bond adhesives, have been developed. In this paper, the second level interconnection (SLI) reliability of edge and corner bonded LF package stackable very thin fine pitch ball grid arrays (PSvfBGAs) was systematic studied using package to board interconnection shear, monotonic 4-point bend, 90° free-drop, and thermal cycling tests. Three materials used in this study were a UV-cured acrylic edge bond adhesive (EBA), and thermal-cured epoxy EBA, and a thermal-cured epoxy corner bond adhesive (CBA). Moreover, the PSvfBGAs without bonding were also tested for comparison. The test results indicate that all the bonding materials increase the mechanical performance of SLIs, especially for drop reliability. On the contrary, the thermal fatigue lives of PSvfBGAs with edge bond acrylic and epoxy are reduced by 38.42% and 8.34%, respectively. In addition to the comparison of maximum shear and bend forces, crosshead displacement, principle strain, drops and thermal cycles to failure between the four test groups, the failure modes and mechanisms of SLIs under various test conditions were analyzed as well.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"1 1","pages":"965-976"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74227208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bio-inspired surface treatment on touch screen panels (TSPs) for adhesion enhancement","authors":"Il Kim, Seunghwan Kim, Inseong You, Haeshin Lee, K. Paik","doi":"10.1109/ECTC.2012.6249102","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249102","url":null,"abstract":"Immersion of substrates in a dilute aqueous solution of bio-inspired building blocks resulted a deposition of polydopamine thin film on the substrate. The Self-polymerization speed measured by ellipsometry was 1.6 nm/hr. Strong catalyst was added in order to enhance the speed. The resulting speed was increased from 1.6 nm/hr to 30 nm/hr. Bio-inspired surface treated PET and ITO-PET substrates with various treatment times were assembled with FPC using commercial acrylic ACF. As a result, adhesion strength between PET substrates and FPC was enhanced dramatically from below 10 gf/cm to over 500 gf/cm even when the treatment time was 5 min. Electrical contact resistance did not show any notable changes. It was presumably due to the sufficiently low thickness (2.5 nm) of bio-inspired thin film on the electrode.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"15 1","pages":"1930-1933"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74529314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integrating through-silicon vias with solder free, compliant interconnects for novel, large area interposers","authors":"I. Shubin, E. Chow, A. Chow, H. Thacker, D. Debruyker, K. Fujimoto, K. Raj, A. Krishnamoorthy, J. Mitchell, J. Cunningham","doi":"10.1109/ECTC.2012.6248838","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248838","url":null,"abstract":"A novel packaging module is described that is based on co-integration of flexible micro-spring interconnects with through silicon copper vias (TSVs) into a passive large area silicon interposer. We report on the packaging test vehicles based on such interposers that are designed to demonstrate a wafer scale integration process to form TSV+spring interconnects with high yield and low resistance. Our goal is to develop a scalable, large area die or MCM packaging platform to enable stress-free, readily reworkable packaging of chips and components with different functionality and technology. We show interposer layouts, share process details and characterization methods.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"2 1","pages":"263-267"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72775592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"All-wet Cu-filled TSV process using electroless Co-alloy barrier and Cu seed","authors":"F. Inoue, T. Shimizu, H. Miyake, R. Arima, S. Shingubara","doi":"10.1109/ECTC.2012.6248926","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248926","url":null,"abstract":"We demonstrated fabrication of Cu-TSV using all-wet process, which has a high potential to apply for the via-last Cu-TSV process. A Co-W alloy diffusion barrier layer was formed on SiO2 layer by electroless plating at 60 °C with Pd nanoparticle catalyst. The barrier layer was thin and continuous throughout a 2 φ × 24 μm TSV and its adhesion strength on SiO2 was as high as that of PVD-Ta. The Co-W alloy layer has undergone an interdiffusion test, which showed a high resistance against Cu diffusion into SiO2 layer. Then, seed layer was formed by electroless Cu deposition on the Co-W alloy layer through displacement reaction. These results reveal a feasibility of all-wet fabrication in a high aspect ratio TSV process.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"11 4","pages":"810-815"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72598226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of phosphorus impact on lead-free BGA solder joint and failure mechanism","authors":"Ming Sun, Muh-ren Lin, T. Chaudhry, R. Lutze","doi":"10.1109/ECTC.2012.6248873","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248873","url":null,"abstract":"Small amounts of phosphorus (P) are often added to lead-free solder balls in ball grid array (BGA) packages to act as an antioxidant during the packaging reflow process. This paper shows that the addition of phosphorus to lead-free solder results in early solder joint failure. Also, we developed the failure mechanism for this phenomenon, which has not previously been understood. Our study shows that the accumulation of phosphorus in the intermetallic compound (IMC) area during the reflow process results in the formation of a thin porous layer at the interface of the IMC layer and the Ni layer of the BGA ball pad. This thin porous layer adversely affects the bond strength of each solder joint. The failure mechanism was developed in terms of factors such as diffusion, deformation-induced stress, crystal structure, thermal stress, and testing environments. Such factors provide an insight into package reliability with regard to the components used in the package and in-service operating conditions (temperature, time, mechanical structure).","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"21 1","pages":"469-476"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73432018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electromigration measurements in thin-film IPD and eWLB interconnections","authors":"R. Frye, Kai Liu, KyawOo Aung, M. P. Chelvam","doi":"10.1109/ECTC.2012.6249004","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249004","url":null,"abstract":"In this paper we describe measurements of electromigration failure times in the metal traces of silicon Integrated Passive Devices (IPDs) and in the redistribution layers of embedded Wafer-Level BGA (eWLB) structures, for both aluminum and copper traces, and for via connections between the two metal layers. The results of the test are used to determine the coefficients of Black's Equation, which is then used to find the extrapolated lifetimes. Maximum current density design guidelines are derived from these results to ensure device reliability in worst-case operation. Some minor differences are observed between these results and similar results for interconnections in conventional ICs. These differences probably arise from the larger conductor cross section and the softer organic dielectrics in IPDs and eWLB packages.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"64 1","pages":"1304-1311"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84288255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cost-effective low-loss flexible optical engine with microlens-imprinted film for high-speed on-board optical interconnection","authors":"T. Shiraishi, T. Yagisawa, T. Ikeuchi, S. Ide, K. Tanaka","doi":"10.1109/ECTC.2012.6249035","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249035","url":null,"abstract":"There is a strong demand for optical interconnection technology to overcome bandwidth bottlenecks in high-end server systems. The interconnection speed in present systems is approaching 10 Gb/s, and higher-speed interconnections over 25 Gb/s are being discussed. To achieve such optical interconnections in commercial production, it is necessary to develop lower-cost and higher-speed optical transceiver modules. We propose a flexible printed circuit optical engine (FPC-OE) with a microlens-imprinted film and a polymer waveguide to achieve low-cost and high-speed operation. The microlens-imprinted film can be produced at low cost by using nanoimprint technology and can drastically reduce the optical loss of the FPC-OE with polymer waveguide. We successfully demonstrated error-free operation at 25 Gb/s with the fabricated optical transceiver that contains an FPC-OE, microlens-imprinted film, and a polymer waveguide.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"27 1","pages":"1505-1510"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84448207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}