{"title":"移动设备用铜柱外露模制FCCSP","authors":"Chang-Yi Lan, C. Hsiao, J. Lau, E. So, B. Ma","doi":"10.1109/ECTC.2012.6248939","DOIUrl":null,"url":null,"abstract":"Due to more build-in functions and smaller form factor requirements, mobile devices are required to have better thermal dissipation performance and thinner IC package profile. In this study, a new package which combines Cu pillar bumps with IC backside exposed-die properties is introduced. Compared with solder bumps, Cu pillar bumps can effectively increase substrate circuit layout density and then reduce substrate layers or shrink package sizes to achieve cost down benefit. Also, compared with traditional over-mold FCCSP, IC backside exposed-die molded FCCSP can effectively eliminate roughly 100μm of package height to achieve thin package requirement. Moreover, exposed-die also can provide better thermal dissipation performance, i.e., Theta JC, when it is attached to an external heat spreader/sink or EMC shielding case. However, compared with solder bumps, Cu pillar bumps (with higher modulus property) will introduce higher mechanical stress to ELK layer and may cause potential ELK cracking issue. Also, compared with traditional over mold package, exposed-die will introduce serious package warpage issue and may cause potential low SMT yield problem. Therefore, the solutions to reduce the mechanical stress from Cu pillar bump to the ELK layer and improve the warpage for exposed-die have aroused lots of attention in semiconductor industry, especially on FCCSP and PoP (Package on Package) recently. In this study, lots of mechanical simulation models and DOE studies used to address how to effectively reduce ELK stress such as adding PI, changing bump shapes, change to DUAL UBM, or adding one RDL layer. Moreover, how substrate or molding compound material selected (such as CTE or Tg adjustment) can effectively reduce package warpage and then eventually improve FCCSP SMT and stacking PoP yields are addressed as well","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"Cu pillar exposed-die molded FCCSP for mobile devices\",\"authors\":\"Chang-Yi Lan, C. Hsiao, J. Lau, E. So, B. Ma\",\"doi\":\"10.1109/ECTC.2012.6248939\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Due to more build-in functions and smaller form factor requirements, mobile devices are required to have better thermal dissipation performance and thinner IC package profile. In this study, a new package which combines Cu pillar bumps with IC backside exposed-die properties is introduced. Compared with solder bumps, Cu pillar bumps can effectively increase substrate circuit layout density and then reduce substrate layers or shrink package sizes to achieve cost down benefit. Also, compared with traditional over-mold FCCSP, IC backside exposed-die molded FCCSP can effectively eliminate roughly 100μm of package height to achieve thin package requirement. Moreover, exposed-die also can provide better thermal dissipation performance, i.e., Theta JC, when it is attached to an external heat spreader/sink or EMC shielding case. However, compared with solder bumps, Cu pillar bumps (with higher modulus property) will introduce higher mechanical stress to ELK layer and may cause potential ELK cracking issue. Also, compared with traditional over mold package, exposed-die will introduce serious package warpage issue and may cause potential low SMT yield problem. Therefore, the solutions to reduce the mechanical stress from Cu pillar bump to the ELK layer and improve the warpage for exposed-die have aroused lots of attention in semiconductor industry, especially on FCCSP and PoP (Package on Package) recently. In this study, lots of mechanical simulation models and DOE studies used to address how to effectively reduce ELK stress such as adding PI, changing bump shapes, change to DUAL UBM, or adding one RDL layer. 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引用次数: 12
摘要
由于更多的内置功能和更小的外形尺寸要求,移动设备需要具有更好的散热性能和更薄的IC封装轮廓。本研究提出一种结合铜柱凸点与IC背面外露模特性的封装方法。与钎料凸点相比,铜柱凸点可以有效地增加衬底电路布局密度,从而减少衬底层数或缩小封装尺寸,从而达到降低成本的效果。此外,与传统的上模FCCSP相比,IC背面外露模FCCSP可以有效地消除约100μm的封装高度,以实现薄封装要求。此外,当外露芯片连接到外部散热片/散热器或EMC屏蔽盒时,还可以提供更好的散热性能,即Theta JC。然而,与钎料凸起相比,铜柱凸起(具有更高的模量)会给ELK层带来更高的机械应力,并可能导致潜在的ELK开裂问题。此外,与传统的过模封装相比,外露的模具将引入严重的封装翘曲问题,并可能导致潜在的低SMT良率问题。因此,如何减小铜柱碰撞对ELK层的机械应力,改善外露模的翘曲,已引起半导体业界的广泛关注,尤其是FCCSP和PoP (Package on Package)。在本研究中,通过大量的力学仿真模型和DOE研究来解决如何有效地降低ELK应力,例如增加PI,改变凹凸形状,更换DUAL UBM,或增加一个RDL层。此外,如何选择基板或成型复合材料(如CTE或Tg调整)可以有效地减少封装翘曲,然后最终提高FCCSP SMT和堆叠PoP的产量
Cu pillar exposed-die molded FCCSP for mobile devices
Due to more build-in functions and smaller form factor requirements, mobile devices are required to have better thermal dissipation performance and thinner IC package profile. In this study, a new package which combines Cu pillar bumps with IC backside exposed-die properties is introduced. Compared with solder bumps, Cu pillar bumps can effectively increase substrate circuit layout density and then reduce substrate layers or shrink package sizes to achieve cost down benefit. Also, compared with traditional over-mold FCCSP, IC backside exposed-die molded FCCSP can effectively eliminate roughly 100μm of package height to achieve thin package requirement. Moreover, exposed-die also can provide better thermal dissipation performance, i.e., Theta JC, when it is attached to an external heat spreader/sink or EMC shielding case. However, compared with solder bumps, Cu pillar bumps (with higher modulus property) will introduce higher mechanical stress to ELK layer and may cause potential ELK cracking issue. Also, compared with traditional over mold package, exposed-die will introduce serious package warpage issue and may cause potential low SMT yield problem. Therefore, the solutions to reduce the mechanical stress from Cu pillar bump to the ELK layer and improve the warpage for exposed-die have aroused lots of attention in semiconductor industry, especially on FCCSP and PoP (Package on Package) recently. In this study, lots of mechanical simulation models and DOE studies used to address how to effectively reduce ELK stress such as adding PI, changing bump shapes, change to DUAL UBM, or adding one RDL layer. Moreover, how substrate or molding compound material selected (such as CTE or Tg adjustment) can effectively reduce package warpage and then eventually improve FCCSP SMT and stacking PoP yields are addressed as well