Electromigration behavior of 3D-IC TSV interconnects

Abstract

The electromigration (EM) behavior of Through Silicon Via (TSV) interconnects used for 3D integration is studied. Impact of the TSV section size on EM lifetime and consideration of increasing metal level thickness are reported. Void nucleates and grows right after TSV, in the adjacent metal level. The TSV section size at metal level interface is critical for high EM performance. Thickness increase of metal level is revealed to not directly increase EM robustness, since irregular void nucleation and growth impact expected performances.