发布求助
文献互助 智能选刊 最新文献

2013 IEEE International Interconnect Technology Conference - IITC最新文献

筛选
英文 中文
Reliable integration of robust porous ultra low-k (ULK) for the advanced BEOL interconnect 可靠集成强大的多孔超低k (ULK)，用于先进的BEOL互连
2013 IEEE International Interconnect Technology Conference - IITC Pub Date : 2013-06-13 DOI: 10.1109/IITC.2013.6615552
K. Han, Seungwook Choi, T. Yim, Seungwook Choi, J. Baek, S. Ahn, N. Lee, Siyoung Choi, Ho-Kyu Kang, E. Jung
{"title":"Reliable integration of robust porous ultra low-k (ULK) for the advanced BEOL interconnect","authors":"K. Han, Seungwook Choi, T. Yim, Seungwook Choi, J. Baek, S. Ahn, N. Lee, Siyoung Choi, Ho-Kyu Kang, E. Jung","doi":"10.1109/IITC.2013.6615552","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615552","url":null,"abstract":"In order to address the increasing RC and reliability challenges at the advanced technology nodes, a new robust ULK was developed that incorporates the bridging carbon atoms (Si-[CH2]x-Si) in p-SiOCH matrix. Its elastic modulus and plasma damage resistance were improved more than 40% at the same dielectric constant than the commercially available ULK. These improvements are attributed to 80% higher atoms that exist in both Si-[CH2]x-Si and Si-CH3 structures with its pore size 23% smaller. Furthermore, its superb properties resulted in 3~4% capacitance reduction, and improvement of TDDB and EM TTF (time to failure) by 2 order and 2~3 times, respectively, on an advanced BEOL vehicle.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"8 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80856828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Grain boundary and surface scattering in interconnect metals 互连金属的晶界和表面散射
2013 IEEE International Interconnect Technology Conference - IITC Pub Date : 2013-06-13 DOI: 10.1109/IITC.2013.6615565
K. Coffey, K. Barmak, T. Sun, A. Warren, B. Yao
{"title":"Grain boundary and surface scattering in interconnect metals","authors":"K. Coffey, K. Barmak, T. Sun, A. Warren, B. Yao","doi":"10.1109/IITC.2013.6615565","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615565","url":null,"abstract":"This work addresses the classical size effect in interconnect metals and presents the theoretical background and quantification of the contributions of grain boundary and surface scattering to the observed resistivity increase in Cu. The results of experimental studies of Cu films and lines are reviewed. The extent to which the experimental data supports the theoretically expected interactions between surface and grain boundary scattering mechanisms will also be discussed.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"49 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77942540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Development and evaluation of a-SiC:H films using a dimethylsilacyclopentane precursor as a low-k Cu capping layer 以二甲基硅环戊烷前驱体作为低钾Cu覆盖层的a- sic:H薄膜的研制与评价
2013 IEEE International Interconnect Technology Conference - IITC Pub Date : 2013-06-13 DOI: 10.1109/IITC.2013.6615577
E. Van Besien, Cong Wang, P. Verdonck, Arjun Singh, Y. Barbarin, J. de Marneffe, K. Vanstreels, H. Tielens, M. Schaekers, M. Baklanov, S. Van Elshocht
{"title":"Development and evaluation of a-SiC:H films using a dimethylsilacyclopentane precursor as a low-k Cu capping layer","authors":"E. Van Besien, Cong Wang, P. Verdonck, Arjun Singh, Y. Barbarin, J. de Marneffe, K. Vanstreels, H. Tielens, M. Schaekers, M. Baklanov, S. Van Elshocht","doi":"10.1109/IITC.2013.6615577","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615577","url":null,"abstract":"Scaling of the Cu interconnect structures requires Cu capping layers with an increasingly lower dielectric constant (K) that still have adequate Cu and moisture barrier properties. In this work, we study the plasma enhanced chemical vapour (PE-CVD) deposition of amorphous silicon carbide films using dimethyl silacyclopentane (DMSCP) as a precursor, resulting in the incorporation of Si-(CH2)n-Si bridges. The effect of process parameters on film characteristics like K, mass density (p), and leakage behaviour is investigated, as well as their relation with the chemical bonding structure. Finally, Cu barrier properties and hermeticity are evaluated.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"10 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84747440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Innovative wafer-based interconnect enabling system integration and semiconductor paradigm shifts 创新的基于晶圆的互连使系统集成和半导体范式转变
2013 IEEE International Interconnect Technology Conference - IITC Pub Date : 2013-06-13 DOI: 10.1109/IITC.2013.6615548
Douglas Yu
{"title":"Innovative wafer-based interconnect enabling system integration and semiconductor paradigm shifts","authors":"Douglas Yu","doi":"10.1109/IITC.2013.6615548","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615548","url":null,"abstract":"In semiconductor world, there is a new paradigm shift from chip-scaling to system-scaling to meet the ever-increasing electronic system demands for performance and functionality, and for reduction of system form factor, power and cost. This shift is also triggered by the fast increasing challenges for industry to sustain Moore's Law. System scaling needs advanced package technologies. Conventionally, package technologies use different tool sets and different materials from those used in wafer fab. Innovative wafer-based technology is proposed here to fabricate advanced packaging that, in turn, enables the system scaling - a new paradigm shift. Another new paradigm shift enabled here is that the advanced packaging shifts from conventional packaging to the innovative wafer-based technology. The innovations cover three major system scaling architecture/technologies: wafer-level-packaging (fan-in and fan-out), through-Si-via (3DIC and interposer) and ultra-thin package-on-package (PoP) for both high performance and mobile devices. We also re-invent microelectronics, continue delivering more advanced electronic systems, and help to sustain Moore's Law.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"30 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87328917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
CVD Mn-based self-formed barrier for advanced interconnect technology 基于CVD锰基自形成势垒的先进互连技术
2013 IEEE International Interconnect Technology Conference - IITC Pub Date : 2013-06-13 DOI: 10.1109/IITC.2013.6615551
Y. Siew, N. Jourdan, Y. Barbarin, J. Machillot, S. Demuynck, K. Croes, J. Tseng, H. Ai, J. Tang, M. Naik, P. Wang, M. Narasimhan, M. Abraham, A. Cockburn, J. Bommels, Z. Tokei
{"title":"CVD Mn-based self-formed barrier for advanced interconnect technology","authors":"Y. Siew, N. Jourdan, Y. Barbarin, J. Machillot, S. Demuynck, K. Croes, J. Tseng, H. Ai, J. Tang, M. Naik, P. Wang, M. Narasimhan, M. Abraham, A. Cockburn, J. Bommels, Z. Tokei","doi":"10.1109/IITC.2013.6615551","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615551","url":null,"abstract":"CVD Mn-based self-formed barrier (SFB) has been evaluated and integrated for reliability and RC delay assessment. Intrinsic TDDB lifetimes were extracted from planar capacitor measurement. A comparable lifetime as the TaN/Ta reference was obtained on SiO2 and porous low-k with a thin oxide liner. Good reliability performance was demonstrated after integration. Compared to conventional barrier, significant RC reduction (up to 45% at 40nm half pitch) and lower via resistance which become more beneficial upon scaling present CVD Mn-based SFB as an attractive candidate for future interconnect technology.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"42 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85440158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Fabrication and electrical characterization of 5×50um through silicon vias for 3D integration 用于3D集成的5×50um硅通孔的制造和电学特性
2013 IEEE International Interconnect Technology Conference - IITC Pub Date : 2013-06-13 DOI: 10.1109/IITC.2013.6615579
B. Bhushan, Minrui Yu, J. Dukovic, L. Wong, Aksel Kitowski, Mun Kvu Park, J. Hua, Shwetha Bolagond, A. Chan, C. Toh, A. Sundarrajan, Niranjan Kumar, S. Ramaswami
{"title":"Fabrication and electrical characterization of 5×50um through silicon vias for 3D integration","authors":"B. Bhushan, Minrui Yu, J. Dukovic, L. Wong, Aksel Kitowski, Mun Kvu Park, J. Hua, Shwetha Bolagond, A. Chan, C. Toh, A. Sundarrajan, Niranjan Kumar, S. Ramaswami","doi":"10.1109/IITC.2013.6615579","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615579","url":null,"abstract":"We present fabrication, electrical characterization, and metrology analysis results of 5×50um TSVs for 3D integration. Specifically, electrical performance of blind TSVs is evaluated by capacitance-voltage (CV) and current-voltage (IV) measurements. Important electrical parameters such as oxide capacitance, minimum TSV capacitance, leakage current, and breakdown voltage are extracted and show good results. The capacitance values also closely match model predictions. The electrical testing data are further verified with a variety of materials analysis techniques.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"90 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75921286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Origin of large contact resistance in organic field-effect transistors 有机场效应晶体管中大接触电阻的来源
2013 IEEE International Interconnect Technology Conference - IITC Pub Date : 2013-06-13 DOI: 10.1109/IITC.2013.6615588
T. Minari, Chuan Liu
{"title":"Origin of large contact resistance in organic field-effect transistors","authors":"T. Minari, Chuan Liu","doi":"10.1109/IITC.2013.6615588","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615588","url":null,"abstract":"The large contact resistance (R<sub>c</sub>) in organic field-effect transistors (OFET) is one of the main limitation factors which prevent the reliable operation and further reduction in device dimensions. In this paper, we report dependence of the R<sub>c</sub> on the gate dielectric materials, which means that the density of charge traps in access region (from contact to channel) of devices plays a primary role for the large R<sub>c</sub> rather than energy mismatch between Fermi level of the metal electrode and valence band level of an organic semiconductor. Based on the finding, we fabricated top-gate OFET devices, the structure of which minimizes access region resistance. Very low R<sub>c</sub> of below 0.1 KΩ cm was successfully achieved in the top-gate OFETs. A field-effect mobility (μ<sub>FET</sub>) of 8.3 cm<sup>2</sup>/V s and near zero threshold voltage (V<sub>T</sub>) were obtained in top-gate devices based on dioctylbenzothienobenzothiophene (C<sub>8</sub>-BTBT).","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"34 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73970782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
48nm Pitch cu dual-damascene interconnects using self aligned double patterning scheme 48nm螺距铜双大马士革互连采用自对准双图案方案
2013 IEEE International Interconnect Technology Conference - IITC Pub Date : 2013-06-13 DOI: 10.1109/IITC.2013.6615589
Shyng-Tsong Chen, Tae-Soo Kim, S. Nam, N. Lafferty, C. Koay, N. Saulnier, Wenhui Wang, Yongan Xu, B. Duclaux, Y. Mignot, M. Beard, Y. Yin, H. Shobha, O. van der Straten, M. He, J. Kelly, M. Colburn, T. Spooner
{"title":"48nm Pitch cu dual-damascene interconnects using self aligned double patterning scheme","authors":"Shyng-Tsong Chen, Tae-Soo Kim, S. Nam, N. Lafferty, C. Koay, N. Saulnier, Wenhui Wang, Yongan Xu, B. Duclaux, Y. Mignot, M. Beard, Y. Yin, H. Shobha, O. van der Straten, M. He, J. Kelly, M. Colburn, T. Spooner","doi":"10.1109/IITC.2013.6615589","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615589","url":null,"abstract":"For sub-64nm pitch interconnects build, it is beneficial to use Self Aligned Double Patterning (SADP) scheme for line level patterning. Usually a 2X pitch pattern was printed first, followed by a Sidewall Image Transfer (SIT) technique to create the 1X pitch pattern. A block lithography process is then used to trim this pattern to form the actual designed pattern. In this paper, 48nm and 45nm pitch SADP build will be used as examples to demonstrate the SADP patterning scheme. General discussions about this patterning scheme will be provided including: 1) the process flow of this technique, 2) benefits of the technique vs. pitch split approach, 3) the design impact and limitation, and 4) the extendability to smaller line pitch build.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"20 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75207762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Demonstration of a 12 nm-half-pitch copper ultralow-k interconnect process 12纳米半间距铜超低k互连工艺的演示
2013 IEEE International Interconnect Technology Conference - IITC Pub Date : 2013-06-13 DOI: 10.1109/IITC.2013.6615593
J. Chawla, R. Chebiam, R. Akolkar, G. Allen, C. Carver, J. Clarke, F. Gstrein, M. Harmes, T. Indukuri, C. Jezewski, B. Krist, H. Lang, A. Myers, R. Schenker, K. Singh, R. Turkot, H. Yoo
{"title":"Demonstration of a 12 nm-half-pitch copper ultralow-k interconnect process","authors":"J. Chawla, R. Chebiam, R. Akolkar, G. Allen, C. Carver, J. Clarke, F. Gstrein, M. Harmes, T. Indukuri, C. Jezewski, B. Krist, H. Lang, A. Myers, R. Schenker, K. Singh, R. Turkot, H. Yoo","doi":"10.1109/IITC.2013.6615593","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615593","url":null,"abstract":"A process to achieve 12 nm half-pitch interconnect structures in ultralow-k interlayer dielectric (ILD) is realized using standard 193 nm lithography. An optimized pattern transfer that minimizes unwanted distortion of ILD features is followed by copper fill. Electrical measurements that validate functionality of the drawn structures are presented.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"83 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76121004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Reliability challenges of through-silicon-via (TSV) stacked memory chips for 3-D integration: From transistors to packages 面向3-D集成的TSV堆叠存储芯片的可靠性挑战:从晶体管到封装
2013 IEEE International Interconnect Technology Conference - IITC Pub Date : 2013-06-13 DOI: 10.1109/IITC.2013.6615583
H.-Y Son, Woong-Sun Lee, Seungkwon Noh, M. Suh, Jae-Sung Oh, Nam-Seog Kim
{"title":"Reliability challenges of through-silicon-via (TSV) stacked memory chips for 3-D integration: From transistors to packages","authors":"H.-Y Son, Woong-Sun Lee, Seungkwon Noh, M. Suh, Jae-Sung Oh, Nam-Seog Kim","doi":"10.1109/IITC.2013.6615583","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615583","url":null,"abstract":"Recently, three-dimensional stacked chip package using through-silicon vias (TSVs) is a major paradigm which leads the transition of semiconductor technology from 2-D to 3-D IC in the electronic industry. However, lots of reliability concerns lie in the developing stage and we should clear away doubtful suspicion prior to mass production of 3-D stacked chip package. In this paper, an overview of reliability issues of 3-D TSV integration is introduced dividing into three categories: zero-level reliability of FEOL (front-end of the-line) such as transistors and capacitors, 1st level of BEOL (back-end of the-line) metallization and TSV interconnections, and 2nd level of micro-bumps of stacked chip interfaces. This paper describes the essential scope of the reliability challenges in 3-D IC packaging technology by dealing with reliability issues from transistor-level of the memory device to package micro-bump level of chip-to-chip interconnections.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"54 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85297907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信