Innovative wafer-based interconnect enabling system integration and semiconductor paradigm shifts

Abstract

In semiconductor world, there is a new paradigm shift from chip-scaling to system-scaling to meet the ever-increasing electronic system demands for performance and functionality, and for reduction of system form factor, power and cost. This shift is also triggered by the fast increasing challenges for industry to sustain Moore's Law. System scaling needs advanced package technologies. Conventionally, package technologies use different tool sets and different materials from those used in wafer fab. Innovative wafer-based technology is proposed here to fabricate advanced packaging that, in turn, enables the system scaling - a new paradigm shift. Another new paradigm shift enabled here is that the advanced packaging shifts from conventional packaging to the innovative wafer-based technology. The innovations cover three major system scaling architecture/technologies: wafer-level-packaging (fan-in and fan-out), through-Si-via (3DIC and interposer) and ultra-thin package-on-package (PoP) for both high performance and mobile devices. We also re-invent microelectronics, continue delivering more advanced electronic systems, and help to sustain Moore's Law.