Reliability challenges of through-silicon-via (TSV) stacked memory chips for 3-D integration: From transistors to packages

Abstract

Recently, three-dimensional stacked chip package using through-silicon vias (TSVs) is a major paradigm which leads the transition of semiconductor technology from 2-D to 3-D IC in the electronic industry. However, lots of reliability concerns lie in the developing stage and we should clear away doubtful suspicion prior to mass production of 3-D stacked chip package. In this paper, an overview of reliability issues of 3-D TSV integration is introduced dividing into three categories: zero-level reliability of FEOL (front-end of the-line) such as transistors and capacitors, 1st level of BEOL (back-end of the-line) metallization and TSV interconnections, and 2nd level of micro-bumps of stacked chip interfaces. This paper describes the essential scope of the reliability challenges in 3-D IC packaging technology by dealing with reliability issues from transistor-level of the memory device to package micro-bump level of chip-to-chip interconnections.