J. Chawla, R. Chebiam, R. Akolkar, G. Allen, C. Carver, J. Clarke, F. Gstrein, M. Harmes, T. Indukuri, C. Jezewski, B. Krist, H. Lang, A. Myers, R. Schenker, K. Singh, R. Turkot, H. Yoo
{"title":"12纳米半间距铜超低k互连工艺的演示","authors":"J. Chawla, R. Chebiam, R. Akolkar, G. Allen, C. Carver, J. Clarke, F. Gstrein, M. Harmes, T. Indukuri, C. Jezewski, B. Krist, H. Lang, A. Myers, R. Schenker, K. Singh, R. Turkot, H. Yoo","doi":"10.1109/IITC.2013.6615593","DOIUrl":null,"url":null,"abstract":"A process to achieve 12 nm half-pitch interconnect structures in ultralow-k interlayer dielectric (ILD) is realized using standard 193 nm lithography. An optimized pattern transfer that minimizes unwanted distortion of ILD features is followed by copper fill. Electrical measurements that validate functionality of the drawn structures are presented.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"83 1","pages":"1-3"},"PeriodicalIF":0.0000,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Demonstration of a 12 nm-half-pitch copper ultralow-k interconnect process\",\"authors\":\"J. Chawla, R. Chebiam, R. Akolkar, G. Allen, C. Carver, J. Clarke, F. Gstrein, M. Harmes, T. Indukuri, C. Jezewski, B. Krist, H. Lang, A. Myers, R. Schenker, K. Singh, R. Turkot, H. Yoo\",\"doi\":\"10.1109/IITC.2013.6615593\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A process to achieve 12 nm half-pitch interconnect structures in ultralow-k interlayer dielectric (ILD) is realized using standard 193 nm lithography. An optimized pattern transfer that minimizes unwanted distortion of ILD features is followed by copper fill. Electrical measurements that validate functionality of the drawn structures are presented.\",\"PeriodicalId\":6377,\"journal\":{\"name\":\"2013 IEEE International Interconnect Technology Conference - IITC\",\"volume\":\"83 1\",\"pages\":\"1-3\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE International Interconnect Technology Conference - IITC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC.2013.6615593\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Interconnect Technology Conference - IITC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2013.6615593","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Demonstration of a 12 nm-half-pitch copper ultralow-k interconnect process
A process to achieve 12 nm half-pitch interconnect structures in ultralow-k interlayer dielectric (ILD) is realized using standard 193 nm lithography. An optimized pattern transfer that minimizes unwanted distortion of ILD features is followed by copper fill. Electrical measurements that validate functionality of the drawn structures are presented.
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