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2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)最新文献

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Analysis and design of silicon bipolar distributed oscillators 硅双极分布振荡器的分析与设计
2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI: 10.1109/VLSIC.2000.852863
A. Hajimiri, Hui Wu
{"title":"Analysis and design of silicon bipolar distributed oscillators","authors":"A. Hajimiri, Hui Wu","doi":"10.1109/VLSIC.2000.852863","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852863","url":null,"abstract":"A systematic approach to design of silicon bipolar distributed oscillators and voltage-controlled oscillators (VCOs) is presented. The operation of the distributed oscillators is analyzed and the general condition for oscillation is derived, resulting in analytical expressions for the frequency and amplitude of the distributed oscillators. Special attention is paid to transmission line modeling that largely determines the performance of the distributed oscillators. A distributed VCO operating at 12 GHz dissipating 13 mW of power is demonstrated. The VCO has a tuning range of 26% with a phase noise of -104 dBc/Hz at 1 MHz offset from the carrier. A second design shows a 17 GHz bipolar distributed oscillator, which dissipates 9 mW of power.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"52 1","pages":"102-105"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85194634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A Si 2-GHz 5-bit LO-phase-shifting downconverter for adaptive antennas 一种用于自适应天线的Si 2 ghz 5位lo移相下变频器
2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI: 10.1109/VLSIC.2000.852853
T. Yamaji, H. Tanimoto, S. Obayashi, Y. Suzuki
{"title":"A Si 2-GHz 5-bit LO-phase-shifting downconverter for adaptive antennas","authors":"T. Yamaji, H. Tanimoto, S. Obayashi, Y. Suzuki","doi":"10.1109/VLSIC.2000.852853","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852853","url":null,"abstract":"A double RC-bridge arbitrary-phase switching circuit is proposed and fabricated as a 2-GHz 5-bit phase shifter using silicon BiCMOS technology. The maximum phase error is 6.5 degrees, which is slightly larger than 1/2 LSB.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"42 1","pages":"66-67"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81872794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A SOI-BiCMOS RF-transmitter for personal digital cellular communication (PDC) 用于个人数字蜂窝通信(PDC)的SOI-BiCMOS射频发射机
2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI: 10.1109/VLSIC.2000.852852
S. Kishore, Glenn Chang, C. Hull
{"title":"A SOI-BiCMOS RF-transmitter for personal digital cellular communication (PDC)","authors":"S. Kishore, Glenn Chang, C. Hull","doi":"10.1109/VLSIC.2000.852852","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852852","url":null,"abstract":"We present a 1-GHz RF-transmitter IC for Personal Digital Cellular Communications (PDC) application in Japan. This IC is mounted in a standard TQFP 32-pin package and it represents the first reported SOI-BiCMOS implementation for cellular usage. The IC utilizes a linear, fully-complex mixing of a UHF signal (650 MHz-750 MHz) and a fixed VHF signal (175 MHz or 250 MHz) to generate spurious-free, I-Q LO (850 MHz-1 GHz). The generated LO carrier is mixed with the /spl pi//4 DQPSK modulated baseband PDC signal in an I/Q upconverter/modulator. The I/Q upconversion signal path includes an upconversion I/Q modulator, a 2-stage linear 40 dB-AGC control circuit, an on-chip balun, and a +1 dBm output driver with on-chip double termination to 50 ohms. The transmitter has better than 50 dB LO-leakage suppression, sideband-rejection of 40 dB, and less than 65 dBc of spurious leakage at the output. The output noise floor is better than -139 dBc/Hz at 10 MHz offset from the carrier in full power mode. The IC dissipates 32 mA of maximum current from a 2.7 V supply.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"99 1","pages":"62-65"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77524925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 60 ns access 32 kByte 3-transistor flash for low power embedded applications 用于低功耗嵌入式应用的60 ns访问32 kByte 3晶体管闪存
2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI: 10.1109/VLSIC.2000.852879
T. Ikehashi, J. Noda, K. Imamiya, M. Ichikawa, A. Iwata, T. Futatsuyama
{"title":"A 60 ns access 32 kByte 3-transistor flash for low power embedded applications","authors":"T. Ikehashi, J. Noda, K. Imamiya, M. Ichikawa, A. Iwata, T. Futatsuyama","doi":"10.1109/VLSIC.2000.852879","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852879","url":null,"abstract":"In this paper, we present a new memory, 3-transistor flash (3-Tr), which is suited to the embedded application. The memory cell has inherited low power the erase/program characteristic of the NAND flash. The cell size of the 32kByte 3-Tr flash, fabricated in a 0.4um NAND flash technology, is 4.36 /spl mu/m/sup 2/. This is about 1/8 of the EEPROM cell size having the same design rule. We also propose two circuit technologies, a low power sensing scheme and a double stage boosting scheme (DSB). The sense scheme aims to reduce the power of the read operation without degrading access time. DSB, on the other hand, improves the power consumption property of the word line (WL) decoder during the program mode. It is also immune to a decrease of the supply voltage Vdd.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"207 1","pages":"162-165"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78249037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 25.9-GHz voltage-controlled oscillator fabricated in a CMOS process 采用CMOS工艺制备的25.9 ghz压控振荡器
2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI: 10.1109/VLSIC.2000.852862
C. Hung, L. Shi, K. O
{"title":"A 25.9-GHz voltage-controlled oscillator fabricated in a CMOS process","authors":"C. Hung, L. Shi, K. O","doi":"10.1109/VLSIC.2000.852862","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852862","url":null,"abstract":"A 25.9-GHz voltage-controlled oscillator (VCO) has been demonstrated using 0.1-/spl mu/m NMOS transistors in a partially scaled CMOS process. The tuning range and output power level are 600 MHz and /spl sim/-22 dBm. The phase noise at a 3-MHz offset is -106 dBc/Hz when the VCO core consumes 24 mW from a 1.5-V supply. This VCO uses a MOS varactor with Q>20 at 26 GHz. Though Q is higher, due to the polysilicon gate depletion effect, the frequency tuning is not monotonic and a mechanism to limit the control voltage range is needed for phase-locked loop (PLL) applications.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"1 1","pages":"100-101"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90284830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
1 GHz leading zero anticipator using independent sign-bit determination logic 使用独立符号位确定逻辑的1ghz超前零预期器
2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI: 10.1109/VLSIC.2000.852888
K.T. Lee, K. Nowka
{"title":"1 GHz leading zero anticipator using independent sign-bit determination logic","authors":"K.T. Lee, K. Nowka","doi":"10.1109/VLSIC.2000.852888","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852888","url":null,"abstract":"The architecture and design methodology of a leading zero anticipator (LZA) using built-in sign-bit determination logic are described. The LZA was implemented in the 1 GHz floating point unit using a 1.8 V, 0.12/0.15(n/p)/spl mu/m L/sub eff/ IBM CMOS technology. The design shows 730 ps of latency and operates at 1 GHz with 5 levels of delayed reset dynamic circuit logic. With the LZA the sign-bit is determined in 446 ps with an area overhead of 8%, whereas a conventional adder generates the sign-bit in 770 ps.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"61 1","pages":"194-195"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77681277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
8-bit/color 1024/spl times/768 microdisplay with analog in-pixel pulse width modulation and retinal averaging offset correction 8位/色1024/spl次/768微显示器，具有模拟像素内脉宽调制和视网膜平均偏移校正
2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI: 10.1109/VLSIC.2000.852840
T. Blalock, N.B. Gaddis, K. Nishimura, T. Knotts
{"title":"8-bit/color 1024/spl times/768 microdisplay with analog in-pixel pulse width modulation and retinal averaging offset correction","authors":"T. Blalock, N.B. Gaddis, K. Nishimura, T. Knotts","doi":"10.1109/VLSIC.2000.852840","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852840","url":null,"abstract":"A liquid-crystal-on-silicon microdisplay based on a 1024/spl times/768 2-D pixel array fabricated in a digital 0.35 /spl mu/m CMOS process displays images with a color depth of 8-bits/color. The pixel pitch is 22 /spl mu/m and the total chip area is 214 mm/sup 2/. Pixel brightness is controlled by modulating the pulse width of the pixel voltage drive signal with an in-pixel analog pulse width modulation (PWM) circuit which utilizes human optic nerve spatio-temporal averaging to eliminate comparator offset. The 16 million transistor chip displays images at a maximum rate of 85 Hz and has a power dissipation of 200 mW from a single 3.3 V supply.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"4 1","pages":"20-23"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76749905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 156 Mbps CMOS laser diode driver for optical burst-mode transmission 用于光突发模式传输的156mbps CMOS激光二极管驱动器
2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI: 10.1109/VLSIC.2000.852882
T. Matsuyama, M. Miki, T. Inoue, N. Murakami, N. Ueno
{"title":"A 156 Mbps CMOS laser diode driver for optical burst-mode transmission","authors":"T. Matsuyama, M. Miki, T. Inoue, N. Murakami, N. Ueno","doi":"10.1109/VLSIC.2000.852882","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852882","url":null,"abstract":"A 3.3 V, 156 Mbps laser diode (LD) driver with a mixed-signal feedback-type automatic optical power control (APC) has been devised for both a quick APC response of 1.5 /spl mu/s and the long holding time of optical power level between burst-data packets of more than 10-s for optical burst-mode transmissions. The LD driver is fabricated in standard triple-well 0.35-/spl mu/m CMOS technology, which can compensate for the degradation of LD optical power, moreover, any external adjustment of optical pulse width is unnecessary.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"30 1","pages":"174-175"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88498344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A CMOS 50% duty cycle repeater using complementary phase blending 采用互补相位混合的CMOS 50%占空比中继器
2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI: 10.1109/VLSIC.2000.852847
K. Nakamura, M. Fukaishi, Y. Hirota, Y. Nakazawa, M. Yotsuyanagi
{"title":"A CMOS 50% duty cycle repeater using complementary phase blending","authors":"K. Nakamura, M. Fukaishi, Y. Hirota, Y. Nakazawa, M. Yotsuyanagi","doi":"10.1109/VLSIC.2000.852847","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852847","url":null,"abstract":"The authors report a duty cycle repeater (DCR) which obtains 50% duty-cycle complementary clock signals from a wide range of input duty-cycle signals from 30% to 70%, even when input signals suffer from timing skew. It features a simple CMOS structure, with a newly developed complementary phase blending architecture and a symmetrical phase blending inverter.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"54 6 1","pages":"48-49"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77099609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
Micromachined microsystems: miniaturization beyond microelectronics 微机械微系统:微型化超越微电子
2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI: 10.1109/VLSIC.2000.852837
K. Najafi
{"title":"Micromachined microsystems: miniaturization beyond microelectronics","authors":"K. Najafi","doi":"10.1109/VLSIC.2000.852837","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852837","url":null,"abstract":"The current state of art in the development of micromachined microsystems is reviewed. Micromachining integrated circuit technologies are increasingly used in combination to develop systems that combine both electronic and non-electronic devices for sensing, actuation, and control. Micromachined systems capable of operating on electronic, mechanical, fluidic, optical, and radiative signals have been developed and commercialized. Several examples of emerging systems with application in microinstrumentation, inertial sensing, biomedical devices, wireless communication, and high-density data storage are presented.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"35 1","pages":"6-13"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83000806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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