采用互补相位混合的CMOS 50%占空比中继器

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI:10.1109/VLSIC.2000.852847

K. Nakamura, M. Fukaishi, Y. Hirota, Y. Nakazawa, M. Yotsuyanagi

{"title":"采用互补相位混合的CMOS 50%占空比中继器","authors":"K. Nakamura, M. Fukaishi, Y. Hirota, Y. Nakazawa, M. Yotsuyanagi","doi":"10.1109/VLSIC.2000.852847","DOIUrl":null,"url":null,"abstract":"The authors report a duty cycle repeater (DCR) which obtains 50% duty-cycle complementary clock signals from a wide range of input duty-cycle signals from 30% to 70%, even when input signals suffer from timing skew. It features a simple CMOS structure, with a newly developed complementary phase blending architecture and a symmetrical phase blending inverter.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"54 6 1","pages":"48-49"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"52","resultStr":"{\"title\":\"A CMOS 50% duty cycle repeater using complementary phase blending\",\"authors\":\"K. Nakamura, M. Fukaishi, Y. Hirota, Y. Nakazawa, M. Yotsuyanagi\",\"doi\":\"10.1109/VLSIC.2000.852847\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors report a duty cycle repeater (DCR) which obtains 50% duty-cycle complementary clock signals from a wide range of input duty-cycle signals from 30% to 70%, even when input signals suffer from timing skew. It features a simple CMOS structure, with a newly developed complementary phase blending architecture and a symmetrical phase blending inverter.\",\"PeriodicalId\":6361,\"journal\":{\"name\":\"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)\",\"volume\":\"54 6 1\",\"pages\":\"48-49\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"52\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2000.852847\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2000.852847","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 52

摘要

作者报告了一种占空比中继器(DCR)，即使在输入信号有时序倾斜的情况下，也能从30% ~ 70%的宽范围输入占空比信号中获得50%占空比的互补时钟信号。它具有简单的CMOS结构，具有新开发的互补相混架构和对称相混逆变器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A CMOS 50% duty cycle repeater using complementary phase blending

The authors report a duty cycle repeater (DCR) which obtains 50% duty-cycle complementary clock signals from a wide range of input duty-cycle signals from 30% to 70%, even when input signals suffer from timing skew. It features a simple CMOS structure, with a newly developed complementary phase blending architecture and a symmetrical phase blending inverter.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

自引率

0.00%

发文量