用于低功耗嵌入式应用的60 ns访问32 kByte 3晶体管闪存

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI:10.1109/VLSIC.2000.852879

T. Ikehashi, J. Noda, K. Imamiya, M. Ichikawa, A. Iwata, T. Futatsuyama

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引用次数: 5

摘要

本文提出了一种适合于嵌入式应用的新型存储器——三晶体管闪存(3-Tr)。该存储单元继承了NAND闪存的低功耗擦除/程序特性。采用0.4um NAND闪存技术制造的32kByte 3-Tr闪存的单元尺寸为4.36 /spl mu/m/sup 2/。这大约是EEPROM单元尺寸的1/8，具有相同的设计规则。我们还提出了两种电路技术，低功耗传感方案和双级升压方案(DSB)。感知方案的目的是在不降低读取时间的前提下降低读取操作的功耗。另一方面，DSB提高了字线解码器在程序模式下的功耗特性。它也不受电源电压Vdd降低的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 60 ns access 32 kByte 3-transistor flash for low power embedded applications

In this paper, we present a new memory, 3-transistor flash (3-Tr), which is suited to the embedded application. The memory cell has inherited low power the erase/program characteristic of the NAND flash. The cell size of the 32kByte 3-Tr flash, fabricated in a 0.4um NAND flash technology, is 4.36 /spl mu/m/sup 2/. This is about 1/8 of the EEPROM cell size having the same design rule. We also propose two circuit technologies, a low power sensing scheme and a double stage boosting scheme (DSB). The sense scheme aims to reduce the power of the read operation without degrading access time. DSB, on the other hand, improves the power consumption property of the word line (WL) decoder during the program mode. It is also immune to a decrease of the supply voltage Vdd.

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2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

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