使用独立符号位确定逻辑的1ghz超前零预期器

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI:10.1109/VLSIC.2000.852888

K.T. Lee, K. Nowka

{"title":"使用独立符号位确定逻辑的1ghz超前零预期器","authors":"K.T. Lee, K. Nowka","doi":"10.1109/VLSIC.2000.852888","DOIUrl":null,"url":null,"abstract":"The architecture and design methodology of a leading zero anticipator (LZA) using built-in sign-bit determination logic are described. The LZA was implemented in the 1 GHz floating point unit using a 1.8 V, 0.12/0.15(n/p)/spl mu/m L/sub eff/ IBM CMOS technology. The design shows 730 ps of latency and operates at 1 GHz with 5 levels of delayed reset dynamic circuit logic. With the LZA the sign-bit is determined in 446 ps with an area overhead of 8%, whereas a conventional adder generates the sign-bit in 770 ps.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"61 1","pages":"194-195"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"1 GHz leading zero anticipator using independent sign-bit determination logic\",\"authors\":\"K.T. Lee, K. Nowka\",\"doi\":\"10.1109/VLSIC.2000.852888\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The architecture and design methodology of a leading zero anticipator (LZA) using built-in sign-bit determination logic are described. The LZA was implemented in the 1 GHz floating point unit using a 1.8 V, 0.12/0.15(n/p)/spl mu/m L/sub eff/ IBM CMOS technology. The design shows 730 ps of latency and operates at 1 GHz with 5 levels of delayed reset dynamic circuit logic. With the LZA the sign-bit is determined in 446 ps with an area overhead of 8%, whereas a conventional adder generates the sign-bit in 770 ps.\",\"PeriodicalId\":6361,\"journal\":{\"name\":\"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)\",\"volume\":\"61 1\",\"pages\":\"194-195\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2000.852888\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2000.852888","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 17

摘要

介绍了一种采用内置符号位确定逻辑的前导零预估器(LZA)的结构和设计方法。LZA采用1.8 V、0.12/0.15(n/p)/spl mu/m L/sub / eff/ IBM CMOS技术，在1ghz浮点单元中实现。该设计显示了730ps的延迟，工作在1ghz，具有5级延迟复位动态电路逻辑。使用LZA，符号位在446 ps内确定，面积开销为8%，而传统加法器在770 ps内生成符号位。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

1 GHz leading zero anticipator using independent sign-bit determination logic

The architecture and design methodology of a leading zero anticipator (LZA) using built-in sign-bit determination logic are described. The LZA was implemented in the 1 GHz floating point unit using a 1.8 V, 0.12/0.15(n/p)/spl mu/m L/sub eff/ IBM CMOS technology. The design shows 730 ps of latency and operates at 1 GHz with 5 levels of delayed reset dynamic circuit logic. With the LZA the sign-bit is determined in 446 ps with an area overhead of 8%, whereas a conventional adder generates the sign-bit in 770 ps.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

自引率

0.00%

发文量