采用CMOS工艺制备的25.9 ghz压控振荡器

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI:10.1109/VLSIC.2000.852862

C. Hung, L. Shi, K. O

{"title":"采用CMOS工艺制备的25.9 ghz压控振荡器","authors":"C. Hung, L. Shi, K. O","doi":"10.1109/VLSIC.2000.852862","DOIUrl":null,"url":null,"abstract":"A 25.9-GHz voltage-controlled oscillator (VCO) has been demonstrated using 0.1-/spl mu/m NMOS transistors in a partially scaled CMOS process. The tuning range and output power level are 600 MHz and /spl sim/-22 dBm. The phase noise at a 3-MHz offset is -106 dBc/Hz when the VCO core consumes 24 mW from a 1.5-V supply. This VCO uses a MOS varactor with Q>20 at 26 GHz. Though Q is higher, due to the polysilicon gate depletion effect, the frequency tuning is not monotonic and a mechanism to limit the control voltage range is needed for phase-locked loop (PLL) applications.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"1 1","pages":"100-101"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"45","resultStr":"{\"title\":\"A 25.9-GHz voltage-controlled oscillator fabricated in a CMOS process\",\"authors\":\"C. Hung, L. Shi, K. O\",\"doi\":\"10.1109/VLSIC.2000.852862\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 25.9-GHz voltage-controlled oscillator (VCO) has been demonstrated using 0.1-/spl mu/m NMOS transistors in a partially scaled CMOS process. The tuning range and output power level are 600 MHz and /spl sim/-22 dBm. The phase noise at a 3-MHz offset is -106 dBc/Hz when the VCO core consumes 24 mW from a 1.5-V supply. This VCO uses a MOS varactor with Q>20 at 26 GHz. Though Q is higher, due to the polysilicon gate depletion effect, the frequency tuning is not monotonic and a mechanism to limit the control voltage range is needed for phase-locked loop (PLL) applications.\",\"PeriodicalId\":6361,\"journal\":{\"name\":\"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)\",\"volume\":\"1 1\",\"pages\":\"100-101\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"45\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2000.852862\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2000.852862","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 45

摘要

在部分缩放的CMOS工艺中，使用0.1-/spl mu/m的NMOS晶体管演示了25.9 ghz压控振荡器(VCO)。调谐范围和输出功率电平为600 MHz和/spl sim/-22 dBm。当VCO核心从1.5 v电源消耗24 mW时，3 mhz偏移的相位噪声为-106 dBc/Hz。该VCO采用26 GHz时Q>20的MOS变容管。虽然Q较高，但由于多晶硅栅极损耗效应，频率调谐不是单调的，锁相环(PLL)应用需要一种限制控制电压范围的机制。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 25.9-GHz voltage-controlled oscillator fabricated in a CMOS process

A 25.9-GHz voltage-controlled oscillator (VCO) has been demonstrated using 0.1-/spl mu/m NMOS transistors in a partially scaled CMOS process. The tuning range and output power level are 600 MHz and /spl sim/-22 dBm. The phase noise at a 3-MHz offset is -106 dBc/Hz when the VCO core consumes 24 mW from a 1.5-V supply. This VCO uses a MOS varactor with Q>20 at 26 GHz. Though Q is higher, due to the polysilicon gate depletion effect, the frequency tuning is not monotonic and a mechanism to limit the control voltage range is needed for phase-locked loop (PLL) applications.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

自引率

0.00%

发文量